EP0211594A2
Expired / Lapsed
EP
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Phase-locked digital synthesiser
Assignee: Libera Developments Ltd
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Filing: 1986-07-29
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Granted: —
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Expires: 2006-07-29
Abstract
Abstract A phase-locked digital synthesiser comprises a voltage-controlled oscillator (6) supplying a frequency divider (7) the output of which is fed to a phase-sensitive detector (9) also receiving an input from a reference oscillator (10). The output of the detector (9) is fed back by a feedback loop to the voltage-controlled oscillator (6) to achieve phase-locking. The divider (7) receives an input from a logic circuit (8) to control the division ratio of the divider (7), the logic circuit being prompted by a control signal which is also used to select one of a plurality of loop filters (12,13) connected for selectable use in the feedback loop from the detector (9) to the voltage controlled oscillator (6), the selected loop filter being appropriate to the prompted division ratio. Other embodiments include compensating means to correct a loop phase error arising from a change in the division ratio.
Inventors
- 👤 John Leslie Haine
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 18:05
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/183; H03L7/187; H03L7/197; H03L7/1972
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
116 words
A phase-locked digital synthesiser comprising a voltage-controlled oscillator supplying a frequency divider the output of which is fed to a phase-sensitive detector also receiving an input from a reference oscillator, the output of the detector being fed back by a feedback loop to the voltage-controlled oscillator to achieve phase-locking, wherein the divider receives an input from a logic circuit to control the division ratio of the divider, the logic circuit being prompted by a control signal which is also used to select one of a plurality of loop filters connected for selectable use in the feedback loop from the detector to the voltage controlled oscillator, the selected loop filter being appropriate to the prompted division ratio.
Claim 2
Dependent Claim
116 words
A phase-locked digital synthesiser comprising a voltage-controlled oscillator supplying a frequency divider the output of which is fed to a phase-sensitive detector also receiving an input from a reference oscillator, the output of the detector being fed back by a feedback loop to the voltage-controlled oscillator to achieve phase-locking, wherein the divider receives an input from a logic circuit to control the division ratio of the divider, the logic circuit being prompted by a control signal which is also used to select one of a plurality of loop filters connected for selectable use in the feedback loop from the detector to the voltage controlled oscillator, the selected loop filter being appropriate to the prompted division ratio.
Claim 3
Dependent Claim
39 words
A synthesiser according to claim 1, wherein a reference timing signal is fed from the reference oscillator to the logic circuit, to ensure that the controlled division selection takes place simultaneously with the rising edges of the reference signal.
Claim 4
Dependent Claim
122 words
A synthesiser according to claim 1 or 2, wherein compensating means are provided to correct a loop phase error arising from a change in the division ratio, the compensationg means comprising comparator means for comparing the phase of the output of the frequency divider with the phase of the reference signal at a sampling time after a predetermined number of reference cycles from the change in the division ratio, means for generating an incremental or decremental correction signal in dependence upon the phase comparison, and means for applying the correction signal to the frequency divider in order to adjust the division ratio, to tend to bring the output of the frequency divider into phase with the reference signal at the sampling time.
Claim 5
Dependent Claim
14 words
A synthesiser according to claim 3, wherein the predetermined number of cycles is two.
Claim 6
Dependent Claim
37 words
A synthesiser according to claim 3 or 4, wherein the correction signal is applied to the frequency divider to adjust the division ratio prevailing over the first reference cycle after the next change in the division ratio.
Claim 7
Dependent Claim
42 words
A synthesiser according to claim 3 or 4, wherein the correction signal is applied to the frequency divider to adjust the division ratio between the beginning of the reference cycle prior to the next change in division ratio and the sampling time.
Claim 8
Dependent Claim
36 words
A synthesiser according to any of claims 3 to 6, wherein the phase detector is an edge-triggered phase detector which detects the rising edges of the pulse trains from the frequency divider and the reference oscillator.
Claim 9
Dependent Claim
36 words
A synthesiser according to any of the preceding claims and used in a burst-mode communications system, the change in division ratio corresponding to a transition from the receive mode to the transmit mode, or vice versa.
Claim 10
Dependent Claim
72 words
A synthesiser according to claim 8, wherein two correction signals are derived, stored and updated, the first correction signal correcting the loop phase error arising from a change in division ratio occuring upon a transition from a receive mode to a transmit mode, and the second correction signal correcting the loop phase error arising from a change in division ratio occurring upon a transition from a transmit mode to a receive mode.
References Cited (Backward Citations)
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