Memory device

Claim 2

A memory devi-e comprising: a) addressing means (30) for cyclically designat­ing different values as addresses for input and output of data per each clock inputted during one operation sequence; and b) memory means (20) having a capacity of plural bits, said memory means (20) cyclically inputting data at different addresses designated by said addressing means (30) and cyclically outputting the data from the designated addresses.

Claim 3

A memory device comprising: a) addressing means (30) for cyclically designat­ing different values as addresses for input and output of data per each clock inputted during each operation sequence; and b) memory means (20) having a capacity of plural bits, said memory means (20) cyclically outputting data stored at different addresses designated by said addressing means (30) and at the same time cyclically writing new data at the designated addresses, said data outputted from said memory means (20) being fed back to the input side of said memory means (20).

Claim 4

A memory device comprising: a) addressing means (30) for cyclically designat­ing different values as addresses for input and output of data per each clock inputted during each operation sequence; and b) memory means (20) having a capacity of plural bits, said memory means (20) cyclically outputting data stored at different addresses designated by said addressing means (30) and at the same time cyclically writing new data at the designated addresses, said data outputted from said memory means (20) being fed back to the input side of said memory means (20).

Claim 5

A memory device comprising: a) addressing means (30) for cyclically designat­ing different values as addresses for input and output of data per each clock inputted of a one-sequence clock signal; b) a flip-flop (31) which inverts its state responsive to the completion of acknowledgement of said one-­sequence clock signal; and c) two memory means (20a, 20b) each having a capacity of plural bits, said two memory means (20a, 20b) having a common data input, different addresses designated by said addressing means (30) being used as a common address input of said two memory means, said two memory means cyclically inputting data at said different addresses designated by said addressing means (30) or outputting data at said different addresses designated, said two memory means (20a, 20b) being such that one is placed in a read state while the other is placed in a write state in response to a designation from said flip-flop (31).

Claim 6

A memory device comprising: a) addressing means (30) for cyclically designat­ing different values as addresses for input and output of data per each clock inputted of a one-sequence clock signal; b) a flip-flop (31) which inverts its state responsive to the completion of acknowledgement of said one-­sequence clock signal; and c) two memory means (20a, 20b) each having a capacity of plural bits, said two memory means (20a, 20b) having a common data input, different addresses designated by said addressing means (30) being used as a common address input of said two memory means, said two memory means cyclically inputting data at said different addresses designated by said addressing means (30) or outputting data at said different addresses designated, said two memory means (20a, 20b) being such that one is placed in a read state while the other is placed in a write state in response to a designation from said flip-flop (31).

Claim 7

A memory device as set forth in claim 2, wherein said memory means (20) is provided with switch means (21) for selectively input said feedback data or said new data.

Claim 8

A memory device as set forth in claim 4, wherein said switch means (21) is comprised of a gate circuit which operates in response to a switching signal.

Claim 9

A memory device as set forth in claim 2, wherein said count value holding means is comprised of a random number generator circuit which does not repeatedly output the same value.

Claim 10

A memory device as set forth in claim 1, wherein said addressing means (30) is comprised of a random number generator circuit which does not repeatedly generate the same value during each cycle.

Claim 11

A memory device as set forth in claim 1, 2 or 3, wherein said addressing means is comprised of a presettable counter (60) to output a value successively increasing or decreasing one by one.

Claim 12

A memory device as set forth in claim 8, wherein said counter (50) outputs a descrete value.

Claim 13

A memory device as set forth in claim 8 or 9, wherein said counter (50) is provided with count value holding means to designate a count value to be outputted.

Claim 14

A memory device as set forth in claim 10, wherein said count value holding means is comprised of a shift register (60).

Claim 15

A memory device as set forth in claim 10, wherein said count value holding means is comprised of read only memory device.