EP0209805A2
Expired / Lapsed
EP
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Semiconductor device having bipolar transistor and insulated gate field effect transistor
Assignee: Hitachi Ltd
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Filing: 1986-07-10
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Granted: —
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Expires: 2006-07-10
Abstract
Abstract A semiconductor device of high integration density and low power consumption prevents the influence of the amplitude of an input signal upon the amplitude of an output signal in such a way that a preceding circuit (C) and a succeeding circuit (D) are endowed with different reference voltages. In an aspect of performance, the semiconductor device is constructed of a circuit which includes a bipolar transistor (26) and an insulated-gate field effect transistor (25, 27, 291, and which operates with reference to one or more voltages (B1), at least one of the reference voltages having a voltage value different from a reference operating voltage (VA) of a preceding circuit (CI which controls the above circuit. In another aspect of performance, first switching means is interposed between a first reference voltage and an input node of a driver circuit, and second switching means is interposed between an output of a preceding circuit and the input of the driver circuit, so that when an output signal of the preceding circuit is at a high level, the second switch is turned "on" while the first switch is turned "off" thereby to produce a still higher potential, and that when the output signal of the preceding circuit is at a low level, the second switch is turned "off" while the first switch is turned "on". The semiconductor device is suited to those circuits of a high-density DRAM and SRAM which use voltage limiters.
Inventors
- 👤 Takao Watanabe
- 👤 Goro Kitukawa
- 👤 Ryoichi Hori
- 👤 Kiyoo Itoh
- 👤 Yoshiki Kawajiri
- 👤 Takayuki Kawahara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 13:46
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10; G11C7/00; G11C7/12; H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/693; H03K19/00; H03K19/01; H03K19/017; H03K19/0175; H03K19/017509; H03K19/017518; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K5/00; H03K5/01; H03K5/08; H03K2217/00; H03K2217/0036
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
121 words
A semiconductor device comprising: a preceding circuit (C) which delivers an output signal of first amplitude in correspondence with an input signal, a power source (VA) which has a first potential to be fed to said preceding circuit (C), and a succeeding circuit (D) which includes at least one bipolar transistor (26) and at least one insulated-gate field effect transistor (25, 27, 29) and to which the output signal of said preceding circuit (C) is applied, said succeeding circuit delivering an output signal of second amplitude larger than the first amplitude in correspondence with the output signal of said preceding circuit (C) and being supplied with a source voltage (Bl) of second potential higher than the first potential (VA). (Fig. 3)
Claim 2
Dependent Claim
121 words
A semiconductor device comprising: a preceding circuit (C) which delivers an output signal of first amplitude in correspondence with an input signal, a power source (VA) which has a first potential to be fed to said preceding circuit (C), and a succeeding circuit (D) which includes at least one bipolar transistor (26) and at least one insulated-gate field effect transistor (25, 27, 29) and to which the output signal of said preceding circuit (C) is applied, said succeeding circuit delivering an output signal of second amplitude larger than the first amplitude in correspondence with the output signal of said preceding circuit (C) and being supplied with a source voltage (Bl) of second potential higher than the first potential (VA). (Fig. 3)
Claim 3
Dependent Claim
112 words
The device of claim 1, wherein said preceding circuit (C) is constructed of a first p-channel MOSFET and a first n-channel MOSFET, gate electrodes of both said MOSFETs being electrically interconnected to form an input node (E) to which the input signal is applied, a source or drain electrode of said first p-channel MOSFET is connected to said power source (VA) having the first potential, the drain or source electrode of said first p-channel MOSFET is connected to a source or drain electrode of said first n-channel MOSFET, to form an output node (F), and -the drain or source electrode of said first n-channel MOSFET is connected to a ground potential (VSS).
Claim 4
Dependent Claim
237 words
The device of claim 1 or 2, wherein said succeeding circuit (D) includes a second p-channel MOSFET (25), a second n-channel MOSFET (27), a third n-channel MOSFET (29) and a first bipolar transistor (26), a gate electrode of said second p-channel MOSFET (25), a gate electrode of said second n-channel MOSFET (27) and a gate electrode of said third n-channel MOSFET (29) are electrically interconnected to form an input node (F) of said succeeding circuit (D) to which the output signal of said preceding circuit (C) is applied, a source or drain electrode of said second p-channel MOSFET (25) and a collector electrode of said first bipolar transistor (26) are electrically connected to each other and to the power source ( B l) having the second potential, the drain or source electrode of said second p-channel MOSFET (25), a source or drain electrode of said second n-channel MOSFET (27) and a base electrode of said first bipolar transistor (26) are electrically interconnected, the drain or source electrode of said second n-channel MOSFET (27) is connected to the ground potential (VSS), an emitter electrode of said first bipolar transistor (26) and a source or drain electrode of said third n-channel MOSFET (29) are electrically interconnected to form an output node (G) which delivers the signal having the second amplitude, and the drain or source electrode of said third n-channel MOSFET (29) is connected to the ground potential (VSS).
Claim 5
Dependent Claim
247 words
The device of claim 2, wherein said succeeding circuit (D) includes a second p-channel MOSFET (51), a second n-channel MOSFET (53), a third n-channel MOSFET (84) and a first bipolar transistor (52), a gate electrode of said second p-channel MOSFET (51), a gate electrode of said second n-channel MOSFET (53) and a gate electrode of said third n-channel MOSFET (84) are electrically interconnected to form an input node (F) of said succeeding circuit (D) to which the output signal of said preceding circuit (C) is applied, a source or drain electrode of said second p-channel MOSFET (51) is connected to a power source .(Bl) which has a third potential lower than the second potential, a collector electrode of said first bipolar transistor (52) is electrically connected to the power source (B2) which has the second potential, the drain or source electrode of said second p-channel MOSFET (51), a source or drain electrode of said second n-channel MOSFET (53) and a base electrode of said first bipolar transistor (52) are electrically interconnected, the drain or source electrode of said second n-channel MOSFET (53) is connected to the ground potential (VSS), an emitter electrode of said first bipolar transistor (52) and a source or drain electrode of said third n-channel MOSFET (84) are electrically interconnected to form an output node (G) which delivers the signal having the second amplitude, the drain or source electrode of said third n-channel MOSFET (84) is connected to the ground potential (VSS). (Fig. 6)
Claim 6
Independent Claim
40 words
The device of any of claims 1 to 4, wherein said preceding circuit (C) is a decoder which decodes an address signal, and said succeeding circuit (D) is a word line driver which drives a word line of a memory.
Claim 7
Dependent Claim
115 words
A semiconductor device comprising: an input node to which an input signal having a first amplitude is applied, an output node which delivers an output signal having an amplitude larger than the first amplitude, first voltage supply means to feed a first voltage to a circuit which drives said output node, second voltage supply means to apply a second voltage to the driver circuit, switching means interposed between said driver circuit and said input node to connect and disconnect them, and voltage application means interposed between said switching means and said driver circuit to establish a potential higher than a high level when the input signal of the first amplitude is at the high level.
Claim 8
Dependent Claim
115 words
A semiconductor device comprising: an input node to which an input signal having a first amplitude is applied, an output node which delivers an output signal having an amplitude larger than the first amplitude, first voltage supply means to feed a first voltage to a circuit which drives said output node, second voltage supply means to apply a second voltage to the driver circuit, switching means interposed between said driver circuit and said input node to connect and disconnect them, and voltage application means interposed between said switching means and said driver circuit to establish a potential higher than a high level when the input signal of the first amplitude is at the high level.
Claim 9
Dependent Claim
46 words
A semiconductor device according to claim 6, wherein the input signal having the first amplitude is a signal of a-decoder which has decoded an address signal, and a word line of a memory is connected to said output node and is driven by said driver circuit.
References Cited (Backward Citations)
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