Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
190 words
A current mirror circuit comprising first and second transistors (1, 2) which have their emitters in common and constitute a differential amplification circuit, third and fourth transistors (3, 4) which have their bases in common, and an input current source (Iin), the emitters of said first and second transistors (1, 2) being connected to a constant current source (Io), the. collector of said second transistor (2) being connected to the bases of said third and fourth transistors (3, 4), the collector of said third transistor (3) being connected to the base of said first transistor (1). the base of said second transistor (2) being connected to a bias node (VB1), the emitters of said third and fourth transistors (3, 4) being connected to a reference power source (Vcc), and the collector of said fourth transistor (4) being connected to an output node (lout), characterised in that the collector of said first transistor (1) is connected to said reference power source (Vcc) through a load resistance (R L ), and by a capacitor (Cl) through which the base and the collector of said first transistor (1) are connected to each other.
Claim 2
Dependent Claim
190 words
A current mirror circuit comprising first and second transistors (1, 2) which have their emitters in common and constitute a differential amplification circuit, third and fourth transistors (3, 4) which have their bases in common, and an input current source (Iin), the emitters of said first and second transistors (1, 2) being connected to a constant current source (Io), the. collector of said second transistor (2) being connected to the bases of said third and fourth transistors (3, 4), the collector of said third transistor (3) being connected to the base of said first transistor (1). the base of said second transistor (2) being connected to a bias node (VB1), the emitters of said third and fourth transistors (3, 4) being connected to a reference power source (Vcc), and the collector of said fourth transistor (4) being connected to an output node (lout), characterised in that the collector of said first transistor (1) is connected to said reference power source (Vcc) through a load resistance (R L ), and by a capacitor (Cl) through which the base and the collector of said first transistor (1) are connected to each other.
Claim 3
Dependent Claim
35 words
A current mirror according to claim 1, wherein said capacitor (Cl) and the junction of said load resistance (R L ) and the collector of said first transistor (1) are connected through a buffer means.
Claim 4
Dependent Claim
57 words
A current mirror according to claim 2, wherein said buffer means is constituted by a fifth transistor (5) which has its base connected to said junction of said load resistance (R L) and the collector of said first transistor (1). its emitter connected to said capacitor (Cl) and its collector connected to said reference power source (Vcc).