EP0209252A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Fine flaw detector for PC boards
Assignee: Visionetics Corp
•
Filing: 1986-06-16
•
Granted: —
•
Expires: 2006-06-16
Abstract
Abstract The circuit board is scanned by a video camera (11) supplying a video processor (12) to provide a serial stream of pixel bits each representative of a picture element within a particular scan line. These serial streams of pixel bits are configured into contiguous patches of n x n picture elements and provided as inputs to logic arrays programmed to detect various types of flaws, by clocking the pixel bits into a RAM (15) with a capacity for 16 scan lines Do to D 15 of 2048 pixel bits per scan line. Each pixel bit position has an address given by a pixel clock driven address counter 16. A transceiver logic circuit 18 loads sixteen sixteen-bit registers (19a-19p) with pixel bits from the RAM (15) and also causes the stored scan lines to move successively from Do to D 15 registers in the RAM (15). When fully loaded, the registers (19a-19p) represent a 16 x 16 bit patches and their 256 outputs are decoded by programmed logic array flaw decoders 21 supplying flaw output signals to an OR-gate 22.
Inventors
- 👤 Richard L. Labinger
- 👤 Natale F. Tinnerino
- 👤 Timothy E. Bryant
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 07:56
CPC Classifications
G; G06; G06T; G06T7/00; G06T7/0002; G06T7/0004; G06T2207/00; G06T2207/10; G06T2207/10016; G06T2207/30; G06T2207/30108; G06T2207/30141
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
138 words
In a system for processing image data on a surface: video scanning means for scanning the surface across its length and width through a plurality of arbitrarily selected scan lines each one of which comprises a plurality of pixels; said video scanning means providing as an output a serial stream of bits each representative of one of said pixels in each of said scan lines; generating means connected to said video scanning means providing n real time outputs of dynamically changing n x n pixel masks of the areas being viewed by said video scanning means; decoder means connected to said generating means programmed to detect one or more flaw types in the areas being viewed by said video scanning means by decoding each of 'the masks provided by said generating means during the scan of the surface.
Claim 2
Dependent Claim
138 words
In a system for processing image data on a surface: video scanning means for scanning the surface across its length and width through a plurality of arbitrarily selected scan lines each one of which comprises a plurality of pixels; said video scanning means providing as an output a serial stream of bits each representative of one of said pixels in each of said scan lines; generating means connected to said video scanning means providing n real time outputs of dynamically changing n x n pixel masks of the areas being viewed by said video scanning means; decoder means connected to said generating means programmed to detect one or more flaw types in the areas being viewed by said video scanning means by decoding each of 'the masks provided by said generating means during the scan of the surface.
Claim 3
Dependent Claim
99 words
In a system according to Claim 1 wherein said generating means comprises: n shift registers with each of said shift registers having n bit storage positions; each of said n bit storage positions having output means such that said n shift registers provide n 2 outputs; formatting means connected between said video scanning means and said n shift registers providing bits representative of said pixels to said shift registers in a manner that the n 2 outputs from said shift registers represent real time n x n pixel masks of the areas being scanned by said video scanning means.
Claim 4
Dependent Claim
117 words
In a system according to Claim 2 wherein said formatting means comprises: random access memory means comprising n registers, each of said n registers including a bit storage position for each of the bits representative of a pixel in a scan line; respective bit storage positions in said n registers being an addressable memory position capable of storing a word of n bits; address counter means for addressing in sequence the memory positions in said n. registers at a predetermined pixel clock rate; transceiver means for reading the bits of the n bit word in an addressed n bit memory position into the respective first bit positions of said n shift registers at said pixel clock rate.
Claim 5
Dependent Claim
53 words
In a system according to Claim 3 wherein said transceiver means further includes, means for writing the bit in the first bit position of each of said shift registers into the next lower bit position of the bit positions of the addressed word in said random access memory at said pixel clock rate.
Claim 6
Dependent Claim
53 words
In a system according to Claim 4 wherein said transceiver means further includes: means connected between said video processor means and said random access memory for writing each new data bit from said video processor means into the addressed bit position of the first of said n registers at said pixel click rate.
Claim 7
Dependent Claim
26 words
In a system according to Claim 5 further comprising: means connected to said address counter means for resetting said address counter means for each scan line.
Claim 8
Dependent Claim
54 words
In a system according to Claim 6 wherein said decoder means comprises; programmable logic array means connected to said n 2 outputs of said n shift registers programmed to decode at said pixel clock rate each n x n pixel mask for a plurality of flaws and providing an output for each flaw detected.
Claim 9
Dependent Claim
47 words
In a system according to Claim 7 wherein said video scanning means comprises; at least one charge coupled array device comprising a plurality of light sensitive elements each of which provides in a serial stream an analog signal representative of the light reflectance of the surface viewed.
Claim 10
Dependent Claim
42 words
In a system according to Claim 8 wherein said video processor means comprises: analog to digital converter means connected to said charged coupled array device providing a digital output of bits each of which represents a pixel area of the surface viewed.
Claim 11
Dependent Claim
99 words
In a system according to Claim 9 wherein said transceiver means comprises: first transmitter (part of transceiver) circuit means connected between respective ones of said n shift registers and said n registers for transferring the addressed word into the first bit positions of said n shift registers; second receiver circuit (part of transceiver) means connected between the first bit positions of said shift registers and the 2nd through n th bit positions of said n registers for transferring the bits to the 2 nd through n th of the addressed word of the bit positions of the addressed word.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.