EP0208186A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A balanced enhancement/depletion mode gallium/arsenide buffer/comparator circuit
Assignee: TDK Micronas GmbH
•
Filing: 1986-06-21
•
Granted: —
•
Expires: 2006-06-21
Abstract
Abstract A complementary depletion/enhancement mode (CDEM) Gallium Arsenide circuit utilizes switching pull-up/pull-down circuits to achieve low power consumption, and makes use of gallium arsenide field effect transistors to achieve high speed. High yield depletion mode field effect transistors are used to implement the sometimes complex complementary logic function in a pass gate configuration. Low yield enhancement mode FETs are used in the closely coupled and spaced tracking circuit. Closely spaced enhancement mode FETs are used because of the likelihood of their having closely matched thresholds.
Inventors
- 👤 Michael Orba Shaver
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 05:39
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
104 words
A balanced enhancement/depletion mode buffer/comparator circuit comprising: plural means for positively pass gating a signal; means for conducting an input signal to one of said plural means for positively pass gating; means for conducting a complementary negative signal of said input signal to another of said plural means for positively pass gating; means for connecting said one of said means and said another of said means respectively each in series with still other of said plural means for positively pass gating; and means for obtaining an output signal and its negative complement from respective said other of said plural means for positively pass gating.
Claim 2
Dependent Claim
104 words
A balanced enhancement/depletion mode buffer/comparator circuit comprising: plural means for positively pass gating a signal; means for conducting an input signal to one of said plural means for positively pass gating; means for conducting a complementary negative signal of said input signal to another of said plural means for positively pass gating; means for connecting said one of said means and said another of said means respectively each in series with still other of said plural means for positively pass gating; and means for obtaining an output signal and its negative complement from respective said other of said plural means for positively pass gating.
Claim 3
Dependent Claim
31 words
The circuit of claim 1, wherein said one of said plural means for positively pass gating comprises a depletion mode field effect transistor whose gate is connected to said input signal.
Claim 4
Dependent Claim
36 words
The circuit of claim 2, wherein said another of said plural means for positively pass gating comprises a depletion mode field effect transistor whose gate is connected to said complementary negative signal of said input signal.
Claim 5
Dependent Claim
41 words
The circuit of claim 3, wherein said still other of said plural means for positively pass gating comprise a pair of enhancement mode field effect transistors whose gates are respectively connected to the sources of said depletion mode field effect transistors.
Claim 6
Dependent Claim
53 words
The circuit of claim 4, further comprising a depletion mode field effect transistor connected in parallel to said depletion mode field effect transistor whose gate is connected to said complementary negative signal, said parallel connected depletion mode field effect transistor having its gate connected to a complementary negative signal of another input signal.
Claim 7
Dependent Claim
125 words
The circuit of claim 4 further comprising a first depletion mode field effect transistor connected with its sou-ce connected to the drain of said depletion mode field effect transistor whose gate is connected to said input signal, a second depletion mode field effect transistor having its drain connected to the drain of said first depletion mode field effect transistor and lts gate connected to both another input signal and the gate of said depletion mode field effect transistor connected to said input signal, and still a third depletion mode field effect transistor whose gate is connected to said another input signal and to the gate of said first depletion mode transistor and whose drain is connected to the source of said second field effect transistor.
Claim 8
Dependent Claim
42 words
The circuit of claim 1, further comprising another means for positively pass gating a signal, said another means connected in parallel with said another of said plural means for positively pass gating and also connected to a negative complement of another input.
Claim 9
Dependent Claim
95 words
The circuit of claim 1, further comprising a first pass gate means connected in series with said one of said means for positively pass gating, a second pass gate means having a common mode with said first pass gate means and also being connected to another input signal and to said one of said means for positively pass gating, and a third pass gate means connected in series with said first and second means and to said input signal, and having a common mode with said another of said plural means for positively pass gating.
Claim 10
Dependent Claim
35 words
The circuit of claim 1, further comprising yet another means for positively pass gating c signal, said yet another means connected in series with said still other of said plural means for positively pass gating.
Claim 11
Dependent Claim
37 words
The circuit of claim 4, further comprising a balancing enhancement mode field effect transistor whose drain is connected to each of the sources of said enhancement mode FETs and whose gate and source are connected to ground.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.