Bidirectional branch prediction and optimization

Claim 1

I. A method for determining in a pipelined computer having memory which of either a first or second instruction to fetch from the memory following the execution in a program of a branch instruction, the first instruction located in memory immediately following the branch instruction, the second instruction located at a positive or negative displacement from the branch instruction, the method comprising: determining the sign of the displacement; fetching the first instruction if the sign of the branch displacement is positive; and fetching the second instruction if the sign of the branch displacement is negative.

Claim 2

A method for performing conditional delayed branching in a computer having a pipeline and running a program by executing a branch instruction which upon the occurrence of a predetermined condition, having true and false states, continues execution with an instruction located at a first address, having a positive or negative displacement from the branch instruction, or continues execution with an instruction located at a second address, being the address of an instruction in a program following the instruction which follows the branch instruction, and depending upon the state of the condition executes an instruction which follows the branch instruction in the pipeline, the method comprising: determining whether the displacement to the first address is pusitive or negative; determining the state of the predetermined condition; executing the instruction which follows the branch instruction in the pipeline if the condition is true and the branch displacement is negative or the condition is false and the branch displacement is positive; and continuing execution of the program at the first address if the condition is true or the second address if the condition is false.

Claim 3

A method for nullifying an instruction which per forms an operation and is capable of generating results, errors, traps and interrupts in a pipelined computer system having memory, the method comprising: fetching the instruction from memory into the instruction pipeline; performing the operation indicated by the instruction, and preventing any results, errors, traps or interrupts generated by fetching or performing the operation indicated by the instruction from being stored in the computer system or affecting the operation of the computer system.

Claim 4

A method for performing conditional delayed branching in a computer having a pipeline and running a program by executing a branch instruction, having a nullify signal with true and false states, which upon the occurrence of a predetermined condition, having true and false states, continues execution with an instruction located at a first address, having a positive or negative branch displacement from the branch instruction, or continues execution with an instruction located at a second address, being the address of an instruction in a program following the instruction which follows the branch instruction, or depending on the state of the condition executes an instruction which follows the branch instruction in the pipeline, the method comprising: determining whether the branch displacement to the first address is positive or negative; determining the state of the predetermined condition; executing the instruction which follows the branch instruction in the pipeline if the nullify signal is false or if the nullify signal is true and either the condition is true and the branch displacement is negative, or the condition is false and the branch displacement is positive; and continuing execution of the program at the first address if the condition is true or the second address if the condition is false.

Claim 5

An apparatus for permitting in a computer system a first instruction, having a nullify signal with a true and false state, to nullify a second instruction, which with a write signal stores the results of the second instruction into the computer or generates errors, traps, and interrupts in the computer system, the apparatus comprising: means for retaining the state of the nullify signal after the execution of the first instruction; and means for qualifying the write signal of the second instruction with the retained state of the nullify signal in order to prevent results from the execution of the instruction from being stored in the computer system or any errors, traps or interrupts from affecting the operation of the computer system.