Control circuit of raster scanning display unit

Claim 2

A control circuit of a raster scanning display unit comprising; (1) a video memory (2) for st_oring display data; (2) a read address generating part for generating a read address of the video memory (2) in synchronism with an address clock; and (3) an address converting part (5) provided between the video memory (2) and the read address generating part, including; (a) a judging part for judging whether or not the area in concern is an area where superposed display is effected, (b) memory means (70) for storing a difference between a head storage address of superposing display data and a head storage address of superposed display data (c) an adder (69) for adding an output signal from said memory means to an output signal from said read address generating part; and (d) selectors (103), (104) each for employing an output signal from said read address generating part and an output signal from said adder (69) as input signals, and delivering any one of said input signals, and furthermore delivering a signal available from said adder (69) when the area in concern is an area where superposed display is effected.

Claim 3

A control circuit of a raster scanning display unit according to claim 1 wherein said judging part consists of; (1) memory means (51), (52) for storing a vertical reference location(e) and a height (c) of a display area where superposed display is effected taking the number of raster clocks as a parameter; (2) memory means (53), (54) for storing a horizontal reference location (d) and a width (b) of a display area where superposed display is effected taking the number of address clock as a parameter; (3) counter means(107) for counting an address clock; (4) counter means (106) for counting an address clock; (5) latch means, said latch means being set a display location reaches said vertical reference location, and being reset after effecting a display corresponding to the height of the display area; and (6) designation means for designating that the area in concern is an area where superposed display is effected when sai_d latch means are set.

Claim 4

A control circuit of a raster scanning display unit according to claim 1 wherein said judging part consists of; (1) first memory means (501) for storing head addresss N1, of a prescribed area in which superposed display data is stored; (2) second memory means (502) for storing a value N 3 yielded by adding 1 to a final address of said prescribed area; (3) third memory means (503) for storing, when a width of an area where superposed display is effected is reduced to the number of clocks being (b), a value N2=N1+b yielded by adding said (b) to said head address N1; (4) fourth memory means (505) for storing a value of yielded by reducting a width of one raster to the number of address clocks; (5) latch means, said latch means being set when an address from the read address generating part gets said N1, and being reset when gets N3; (6) fifth memory means for storing said N1 when said latch means is reset, and storing a value yielded by adding y to the original value every!time a raster clock is issued after said latch means is set; (7) sixth memory means for storing said N2 when said latch means is set, and for storing a value yielded by adding y to the original value every time a raster clock is issued after said latch means is set; (8) a first comparator (507) for comparing an output signal from said fifth memory means with an address signal from said read address generating part; (9) a second comparator (109) for comparing an output signal from said sixth memory means with an address signal from said read address generating part; (10) a latch means (519), said latch means being set by a coincidence signal from said first comparator while being reset by a coincidence signal from said second comparator; and (11) designation means for designating that the area in concern is an adder where superposed display is effected where said two latch means are both set.