EP0205728A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Arrangement of input-output pins of an integrated circuit package
Assignee: Toshiba Corp
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Filing: 1986-01-17
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Granted: —
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Expires: 2006-01-17
Abstract
Abstract In an integrated circuit chip (1) in accordance with the present invention, two kinds of power supplies (3,5) that are used for operating the integrated circuit chip (1) and a ground which constitutes a source power supply which is common to the two power supplies are connected to the input-output pins (8-21) that are provided on the package for the chip (1). Here, the input-output pins (10, 12) connected to the power supplies (3, 5) are adjacently arranged on both sides of the input-output pin (11) that is connected to the ground. Consequently, the lengths of the power supply current loops that are formed between the power supply terminals and the ground terminal are designed to become short, and hence the high frequency radiation from the loops reduced accordingly.
Inventors
- 👤 Koji 1-2 Ooki-Coopo 1-13-4 Furuichiba Nakanishi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 12:11
CPC Classifications
H; H10; H10W; H10W44/00; H10W44/601; H10W70/00; H10W70/40
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
89 words
An arrangement of I/O pins for an IC package which includes at least digital circuits, comprising: (a) a first set of I/O pins which are to be connected to each of a plurality of power supplies required for the operation of the IC; and (b) a second I/O pin which is to be connected to at least one of the source power supplies that correspond to the plurality of power supplies. (c) said first set of I/O pins and said second I/O pin being arranged adjacent to each other.
Claim 2
Dependent Claim
89 words
An arrangement of I/O pins for an IC package which includes at least digital circuits, comprising: (a) a first set of I/O pins which are to be connected to each of a plurality of power supplies required for the operation of the IC; and (b) a second I/O pin which is to be connected to at least one of the source power supplies that correspond to the plurality of power supplies. (c) said first set of I/O pins and said second I/O pin being arranged adjacent to each other.
Claim 3
Dependent Claim
31 words
An arrangement of I/O pins for an IC package as claimed in Claim 1, in which said first and second I/O pins are arranged at positions nearest to the digital circuits.
Claim 4
Dependent Claim
23 words
An arrangement of I/O pins for an IC package as claimed in Claim 2, in which the digital circuits comprise an IC chip.
Claim 5
Dependent Claim
51 words
An arrangement of I/O pins for an IC package as claimed in Claim 1, in which said second I/O pin is arranged adjacent to said first set of I/O pins when the source power supply is shared by more than two power supplies out of the plurality of the power supplies.
Claim 6
Dependent Claim
45 words
An arrangement of I/O pins for an IC package as claimed in Claim 1, in which said second I/O pin is arranged between said first I/O pins when the source power supply is shared by two power supplies out of the plurality of power supplies.
Claim 7
Dependent Claim
81 words
An arrangement of I/O pins for an IC circuit package as claimed in Claim 1, in which the source power supplies are provided for each of the plurality of power supplies, and the second set of I/O pins that are connected to each of said source power supplies and the first set of I/O pins that are connected to each of the plurality of the power supplies are arranged adjacent to each other for each pair of power supply and ground.
Claim 8
Dependent Claim
33 words
An arrangement of I/O pins for an IC package as claimed in Claim 1, in which each of the power supplies has a bypass capacitor in the neighborhood of said first I/O pins.
Claim 9
Dependent Claim
24 words
An arrangement of I/O pins for an IC package as claimed in Claim 1, in which the IC package is a DIP type package.
Claim 10
Dependent Claim
23 words
An arrangement of I/O pins for an IC package as claimed in Claim 1, in which the IC package is a flat package.
Claim 11
Dependent Claim
25 words
An arrangement of I/O pins for an IC package as claimed in Claim 1, in which the IC package is a chip carrier type package.
Claim 12
Dependent Claim
28 words
ll. An arrangement of I/O pins for an IC circuit package as claimed in Claim 1, in which the IC package is a pin grip array type package.
Claim 13
Dependent Claim
103 words
An IC package which includes at least digital circuits, comprising: (a) a first set of I/O pins that are to be connected to each of at least more than two power supplies used for operating the IC; and (b) a second IC pin that is to be connected to at least one source power supply that correspond to the more than two power supplies. (c) said first set of I/O pins and said second I/O pin being arranged so as to have minimum lengths for the power supply current loops formed between said first set of I/O pins to said second I/O pin.
Claim 14
Dependent Claim
103 words
An IC package which includes at least digital circuits, comprising: (a) a first set of I/O pins that are to be connected to each of at least more than two power supplies used for operating the IC; and (b) a second IC pin that is to be connected to at least one source power supply that correspond to the more than two power supplies. (c) said first set of I/O pins and said second I/O pin being arranged so as to have minimum lengths for the power supply current loops formed between said first set of I/O pins to said second I/O pin.
Claim 15
Dependent Claim
26 words
An IC package as claimed in Claim 12, in which said first set of I/O pins and said second pin are arranged adjacent to each other.
Claim 16
Dependent Claim
31 words
An arrangement of I/O pins for an IC package as claimed in Claim 13, in which said first and second I/O pins are arranged at positions nearest to the digital circuits.
Claim 17
Dependent Claim
23 words
An arrangement of I/O pins for an IC package as claimed in Claim 14, in which the digital circuits comprise an IC chip.
Claim 18
Dependent Claim
33 words
An arrangement of I/O pins for an IC package as claimed in Claim 15, in which each of the power supplies has a bypass capacitor in the neighborhood of said first I/O pins.
Claim 19
Dependent Claim
53 words
An arrangement of I/O pins for an IC package as claimed in Claim 16, in which the power supply current loops are power current loops for high frequency component formed among the power supplies, said first I/O pins, the IC chip, said second I/O pin, the source power supplies, and the bypass capacitors.
Claim 20
Dependent Claim
59 words
An IC package as claimed in Claim 10, in which said first set of I/O pins comprise more than two I/O pins that are to be connected respectively to more than two power supplies, and said second I/O output pin is to be connected to one source power supply that corresponds commonly to the more than two power supplies.
Claim 21
Dependent Claim
64 words
An IC package as claimed in Claim 13, in which said first set of I/O pins comprise two I/O pins that are to be connected respectively to two supplies, said second I/O pin is to be connected to one source power supply that corresponds commonly to the two power supplies, and said second I/O pin is arranged between said first set of I/O pins.
Claim 22
Dependent Claim
86 words
An IC package as claimed in Claim 13, in which said first set of I/O pins are to be connected respectively to the plurality of power supplies, said second I/O pin comprise a plurality of I/O pins that are to be connected respectively to the plurality of source power supplies that correspond respectively to the plurality of power supplies, said first set of I/O pins and said second set of I/O pins are arranged adjacent to each other for each pair of power supply and ground.
References Cited (Backward Citations)
No citation records indexed.
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