EP0203728A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Graphics picture element data byte processor
Assignee: International Business Machines Corp
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Filing: 1986-04-28
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Granted: —
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Expires: 2006-04-28
Abstract
Abstract A pixel (picture element data byte) processor - (10) includes a plurality of pixel slice processors (11, 12, 13) and the architecture is arranged so that the pixel length is extendible by merely increasing the number of pixel slice processors. Each of the pixel slice processors is firstly interconnected with other pixel slice processors, and includes a plurality of registers, gates and multiplexers for selectively presenting to a processing means data derived from a variety of sources, including a frame buffer. The output of the processing means can be stored back in the frame buffer or directed to one or more registers in the associated pixel slice processor or/and to registers in other pixel slice processors. SIMD (single instruction, multiple data) operation is accomplished for pixel lengths which are equal to or larger than the bit capacity of the pixel slice processors.
Inventors
- 👤 Leon Lumelsky
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 12:53
CPC Classifications
G; G06; G06T; G06T1/00; G06T1/20
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
175 words
A pixel (picture element data byte) processor - (10) comprising: a plurality of unit processors (11, 12, 13), a first data bus (50) connected to all said unit processors, a control memory (20) with outputs connected to all said unit processors, a frame buffer (30) with a bidirectional data path - (1 B, 2B, ...KB) to and from each of said unit processors, each said unit processor including: source (SMR, SR) and destination (DMR, DR) operand registers each of n-bit length and each coupled to said bidirectional data path, processing means (SAND, DAND, SMUX, DMUX, 200, T) with an input from each of said operand registers for processing data derived from said operand registers to produce n-bit output data, a data latch (LA) responsive to said n-bit output data of said processing means, and connecting means coupling said data latch to said bidirectional data path and to said first data bus, whereby extensions of pixel length are accommodated by adding an additional unit processor for each extension of pixel length of n bits or less.
Claim 2
Dependent Claim
175 words
A pixel (picture element data byte) processor - (10) comprising: a plurality of unit processors (11, 12, 13), a first data bus (50) connected to all said unit processors, a control memory (20) with outputs connected to all said unit processors, a frame buffer (30) with a bidirectional data path - (1 B, 2B, ...KB) to and from each of said unit processors, each said unit processor including: source (SMR, SR) and destination (DMR, DR) operand registers each of n-bit length and each coupled to said bidirectional data path, processing means (SAND, DAND, SMUX, DMUX, 200, T) with an input from each of said operand registers for processing data derived from said operand registers to produce n-bit output data, a data latch (LA) responsive to said n-bit output data of said processing means, and connecting means coupling said data latch to said bidirectional data path and to said first data bus, whereby extensions of pixel length are accommodated by adding an additional unit processor for each extension of pixel length of n bits or less.
Claim 3
Dependent Claim
53 words
A processor as claimed in claim 1 which further includes: a second source and second destination register each of n-bit length and each coupled to said bidirectional data path, source and destination multiplexers each connected between said processing means said source and second source registers and said destination and second destination registers, respectively.
Claim 4
Dependent Claim
82 words
A processor as claimed in claim 1 which further includes: a second source and second destination register each of n-bit length and each coupled to said bidirectional data path, source and destination multiplexers and source and destination AND gates, said source AND gate coupled between said source and second source registers and said source multiplexer, said destination AND gate coupled between said destination and second destination registers and said destination multiplexer, said source and destination multiplexers each connected to said processing means.
Claim 5
Dependent Claim
33 words
A processor as claimed in any one of the preceding claims in which said connecting means includes a bidirectional transceiver coupled between said output of said data latch and said first data bus.
Claim 6
Dependent Claim
52 words
A processor as claimed in any one of the preceding claims which further includes a transceiver coupled between said data latch and said processing means, said transceiver having a first port coupled to said processing means and a second port coupled in common to said data latch and a host data bus.
Claim 7
Dependent Claim
50 words
A processor as claimed in claim 5 in which said processing means is a random access memory means addressable by said source and destination operand registers for providing an output to said data latch through said transceiver and responsive to data provided through said transceiver from said host data bus.
Claim 8
Dependent Claim
73 words
A processor as claimed in any one of the preceding claims in which said control memory has at least two groups of outputs, a first group of outputs commonly connected to all said unit processors, and a second group of outputs uniquely connected to different ones of said unit processors, and in which said source and destination operand registers are enabled by signals within said first group of outputs from said control memory.
Claim 9
Dependent Claim
71 words
A processor as claimed in claim 2 in which said control memory has at least two groups of outputs, a first group of outputs commonly connected to all said unit processors, and a second group of outputs uniquely connected to different ones of said unit processors, said source, second source and destination and second destination operand registers are enabled by signals within said first group of outputs from said control memory.
Claim 10
Dependent Claim
91 words
A processor as claimed in claim 3 in which said control memory has at least two groups of outputs, a first group of outputs commonly connected to all said unit processors, and a second group of outputs uniquely connected to different ones of said unit processors, said source, second source and destination and second destination operand registers are enabled by signals within said first group of outputs from said control memory and said source and destination multiplexers are controlled by signals within said first group of outputs from said control memory.
Claim 11
Dependent Claim
32 words
A processor as claimed in claim 1 in which said first data bus is connected in common to all said unit processors and through a master transceiver to a host data bus.
Claim 12
Dependent Claim
41 words
A processor as claimed in claim 1 in which said first data bus has a group of conductors uniquely dedicated to each unit processor and all said groups of conductors are connected through a master transceiver to a host data bus.
Claim 13
Dependent Claim
215 words
A graphic processor for single instruction multiple data operations on k pixels simultaneously, where k is an integer greater than one, which processor is also easily expandable in terms of pixel length and can efficiently handle conditional operations requiring efficient interpixel communications comprising: a plurality of n frame buffers, each buffer storing data of k bit width, said plurality of frame buffers arranged in groups of i frame buffers per group, where n and i are each integers greater than one and i is an integer less than n to provide n/i groups of frame buffers, a plurality of pixel slice processors, each operating on data of i bit width, said plurality of pixel slice processors arranged in n/i groups of k processors per group where each frame buffer group has a corresponding pixel slice processor group, data path means to provide for: i) bidirectional data flow within a group between said frame buffers and said pixel slice processors, ii) data flow between pixel slice processors of a group, and iii) data flow between corresponding pixel slice processors of different groups, whereby computations requiring intra pixel carries and conditional computations requiring inter pixel communications are provided for on said data path means and extensions of pixel length are handled by increases in the integer n.
Claim 14
Dependent Claim
215 words
A graphic processor for single instruction multiple data operations on k pixels simultaneously, where k is an integer greater than one, which processor is also easily expandable in terms of pixel length and can efficiently handle conditional operations requiring efficient interpixel communications comprising: a plurality of n frame buffers, each buffer storing data of k bit width, said plurality of frame buffers arranged in groups of i frame buffers per group, where n and i are each integers greater than one and i is an integer less than n to provide n/i groups of frame buffers, a plurality of pixel slice processors, each operating on data of i bit width, said plurality of pixel slice processors arranged in n/i groups of k processors per group where each frame buffer group has a corresponding pixel slice processor group, data path means to provide for: i) bidirectional data flow within a group between said frame buffers and said pixel slice processors, ii) data flow between pixel slice processors of a group, and iii) data flow between corresponding pixel slice processors of different groups, whereby computations requiring intra pixel carries and conditional computations requiring inter pixel communications are provided for on said data path means and extensions of pixel length are handled by increases in the integer n.
Claim 15
Dependent Claim
100 words
A processor as claimed in claim 12 in which said data path means comprises: a first set of data paths in each group coupling first i/o ports of said pixel slice processors to i/o ports of said frame buffers, a second set of data paths for intra group communication coupling second i/o ports of pixel slice processors in a group to each other to provide for inter pixel data communication, and a third set of data paths for inter group communication coupling third i/o ports of corresponding pixel slice processors in different groups to provide for intra pixel data communication.
Claim 16
Dependent Claim
50 words
A processor as claimed in claim 13 in which said first set of data paths in each group includes k bidirectional data paths, arranged in groups of i conductors, each group of i conductors coupling one of said k pixel slice processors to said i frame buffers of a group.
Claim 17
Dependent Claim
70 words
A processor as claimed in any one of claims 12, 13 or 14 which further includes: a plurality of circuit boards, one for each group, in which each of said groups of pixel slice processors are located on a different one of said circuit boards, and an inter board bus to provide that portion of said data path means for data flow between corresponding pixel slice processors of different groups.
Claim 18
Dependent Claim
77 words
A processor as claimed in any one of claims 12, 13, 14, or 15 which further includes a tri-port transceiver for each pixel slice processor, a first port coupled to bus internal to the associated pixel slice processor, a second port coupled over a portion of said data path means to transceivers associated with different pixel slice processors within a group and a third port coupled to transceivers associated with corresponding pixel slice processors in different groups.
Claim 19
Dependent Claim
67 words
A processor as claimed in any one of claims 12, 13, 14, 15 or 16 which further includes a five port transceiver for each pixel slice processor, a first port coupled over a bus in said data path means to transceivers associated with corresponding pixel slice processors in different groups, and second through fifth ports coupled to transceivers associated with different pixel slice processors within a group.
Claim 20
Independent Claim
383 words
A method of implementing a Z-buffer algorithm on a pixel processor, wherein pixel information includes a depth portion, said pixel processor including: a plurality of pixel slice processors, a first data bus connected to all said pixel slice processors, a frame buffer with a bidirectional data path to/from each of said pixel slice processors, each said pixel slice processor including: source, second source, destination and second destination operand registers each of n-bit length and each coupled to said bidirectional data path, a source AND gate with an input from said source and second source operand registers and an output, a destination AND gate with inputs from said destination and second destination operand registers and an output, source and destination multiplexers each with respective inputs from said bidirectional data path, operand and second operand registers and AND gates, processing means with an input from each of said multiplexers for processing data derived from said multiplexers to produce n-bit output data, a data latch responsive to said n-bit output data of said processing means, and connecting means coupling said data latch to said bidirectional data path and to said first data bus, said method comprising the steps of: a) storing source pixel information in corresponding registers of a plurality of said pixel slice processors, b) storing destination pixel information in corresponding registers of a plurality of pixel slice processors, c) comparing said depth information portion of said pixel information in at least two different pixel slice processors to derive in each of at least two pixel slice processors an equality, lesser or greater relation between said source and destination depth portion of pixel information, d) combining said relation information to produce a single result indicating equality, lesser or greater relation, e) transferring said single result to a corresponding operand register in each of said pixel slice processors, f) complementing said single result and transferring said complement to a different corresponding operand register in each of said pixel slice processors, g) ANDing said single result with source or destination pixel information and Anding said complement with destination or source pixel information in each pixel slice processor, and h) applying the results of step g) to said processing means to produce either said source or destination pixel information in dependence on the result of said comparing step.
Claim 21
Independent Claim
383 words
A method of implementing a Z-buffer algorithm on a pixel processor, wherein pixel information includes a depth portion, said pixel processor including: a plurality of pixel slice processors, a first data bus connected to all said pixel slice processors, a frame buffer with a bidirectional data path to/from each of said pixel slice processors, each said pixel slice processor including: source, second source, destination and second destination operand registers each of n-bit length and each coupled to said bidirectional data path, a source AND gate with an input from said source and second source operand registers and an output, a destination AND gate with inputs from said destination and second destination operand registers and an output, source and destination multiplexers each with respective inputs from said bidirectional data path, operand and second operand registers and AND gates, processing means with an input from each of said multiplexers for processing data derived from said multiplexers to produce n-bit output data, a data latch responsive to said n-bit output data of said processing means, and connecting means coupling said data latch to said bidirectional data path and to said first data bus, said method comprising the steps of: a) storing source pixel information in corresponding registers of a plurality of said pixel slice processors, b) storing destination pixel information in corresponding registers of a plurality of pixel slice processors, c) comparing said depth information portion of said pixel information in at least two different pixel slice processors to derive in each of at least two pixel slice processors an equality, lesser or greater relation between said source and destination depth portion of pixel information, d) combining said relation information to produce a single result indicating equality, lesser or greater relation, e) transferring said single result to a corresponding operand register in each of said pixel slice processors, f) complementing said single result and transferring said complement to a different corresponding operand register in each of said pixel slice processors, g) ANDing said single result with source or destination pixel information and Anding said complement with destination or source pixel information in each pixel slice processor, and h) applying the results of step g) to said processing means to produce either said source or destination pixel information in dependence on the result of said comparing step.
References Cited (Backward Citations)
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