EP0203700A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Logic level translators
Assignee: Advanced Micro Devices Inc
•
Filing: 1986-04-18
•
Granted: —
•
Expires: 2006-04-18
Abstract
Abstract A logic level translator having high switching speeds for converting ECL logic levels into TTL logic levels includes a pair of input transistors for receiving ECL input logic level signals and an output transistor for generating TTL output logic level signals. Current mirror transistors are interconnected between the input transistors and the output transistor for turning on and off the output transistor. High-pass networks are coupled to the current mirror transistors for increasing its transient response so as to facilitate turning on and off quickly the output transistor. The TTL output logic levels have a relatively small propagation delay responsive to transitions of the ECL input logic level signals.
Inventors
- 👤 Bertrand Jeffery Williams
- 👤 Stanley Wilson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 04:43
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K19/00; H03K19/01; H03K19/013; H03K19/0136; H03K19/0175; H03K19/018; H03K19/01806; H03K19/01812
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
306 words
A logic level translator having high switching speeds for converting ECL logic levels to TTL logic levels, said translator comprising: a first and second input transistors having their collectors connected to a supply potential, the bases of said first and second transistors being adapted to receive ECL input logic level signals; a third transistor having its base and collector connected together and to the emitter of said first transistor; a fourth transistor having its base and collector connected together and to the emitter of said second transistor; a current mirror formed of a pair of fifth and sixth transistors having their emitters connected together and to a ground potential; a first resistor and a first capacitor being connected in parallel with ' its one end connected to the emitter of said third transistor and its other end connected to the collector of said fifth transistor; a second resistor and a second capacitor being connected in parallel with its one end connected to the emitter of said fourth transistor and its other end connected to the collector of said sixth transistor; an inverter transistor having its base connected to the collector of said sixth transistor, its collector connected to the supply potential via a load resistor, and its emitter connected to the ground potential; circuit means for generating large transient drive current differences at the bases of said fifth and sixth transistors so as to facilitate turning on quickly one of said fifth and sixth transistors and turning off quickly the other one of said fifth and sixth transistors; and said base of said inverter transistor being responsive to said transient drive current differences at the bases of said fifth and sixth transistors so as to create a very fast output response at TTL logic levels on its collector during transitions of the ECL input logic levels.
Claim 2
Dependent Claim
306 words
A logic level translator having high switching speeds for converting ECL logic levels to TTL logic levels, said translator comprising: a first and second input transistors having their collectors connected to a supply potential, the bases of said first and second transistors being adapted to receive ECL input logic level signals; a third transistor having its base and collector connected together and to the emitter of said first transistor; a fourth transistor having its base and collector connected together and to the emitter of said second transistor; a current mirror formed of a pair of fifth and sixth transistors having their emitters connected together and to a ground potential; a first resistor and a first capacitor being connected in parallel with ' its one end connected to the emitter of said third transistor and its other end connected to the collector of said fifth transistor; a second resistor and a second capacitor being connected in parallel with its one end connected to the emitter of said fourth transistor and its other end connected to the collector of said sixth transistor; an inverter transistor having its base connected to the collector of said sixth transistor, its collector connected to the supply potential via a load resistor, and its emitter connected to the ground potential; circuit means for generating large transient drive current differences at the bases of said fifth and sixth transistors so as to facilitate turning on quickly one of said fifth and sixth transistors and turning off quickly the other one of said fifth and sixth transistors; and said base of said inverter transistor being responsive to said transient drive current differences at the bases of said fifth and sixth transistors so as to create a very fast output response at TTL logic levels on its collector during transitions of the ECL input logic levels.
Claim 3
Dependent Claim
41 words
A logic level translator as claimed in Claim 1, wherein said circuit means includes a first high-pass network formed of a third resistor and a third capacitor and a second high-pass network formed of a fourth resistor and a fourth capacitor.
Claim 4
Dependent Claim
121 words
A logic level translator as claimed in Claim 2, wherein one end of said fourth resistor is connected to the base of the fifth transistor and one end of the fourth capacitor, the other end of the fourth resistor being connected to one end of the third resistor, the junction of the third and fourth resistors being joined to the collector of the fifth transistor, the other end of the third resistor being connected to the base of the sixth transistor and to one end of the third capacitor, the other end of the third capacitor being connected to the emitter of the third transistor, the other end of the fourth capacitor being connected to the emitter of the fourth transistor.
Claim 5
Dependent Claim
21 words
A logic level translator as claimed in Claim 1, wherein said first through sixth transistors are bipolar transistors of the NPN-type.
Claim 6
Dependent Claim
17 words
A logic level translator as claimed in Claim 1, wherein said inverter transistor is a Schottky transistor.
Claim 7
Dependent Claim
16 words
A logic level translator as claimed in Claim 1, wherein said supply potential is +5.0 volts.
Claim 8
Dependent Claim
34 words
A logic level translator as claimed in Claim 1, wherein the ECL input logic level signals are +5 volts representing the logic level "1" and 5 volts minus 750mv representing the logic level "0".
Claim 9
Dependent Claim
32 words
A logic level translator as claimed in Claim 1, wherein the TTL output logic level signals are +5 volts representing the logic level "1" and 0.25 volts representing the logic level "0".
Claim 10
Dependent Claim
24 words
A logic level translator as claimed in Claim 1, wherein said translator is formed on a single silicon chip of a semiconductor integrated circuit.
Claim 11
Dependent Claim
112 words
A logic level translator having high switching speeds for converting ECL logic levels into TTL logic levels, said translator comprising: input means for receiving ECL input logic level signals; output means formed of an output transistor being adapted to provide TTL output logic level signals; current mirror means interconnected between said input means and said output means for turning on and off said output transistor; and circuit means for increasing transient response of said current mirror means so as to facilitate turning on and off quickly said output transistor whereby the TTL output logic levels have a relatively small propagation delay in response to transitions of the ECL input logic level signals.
Claim 12
Dependent Claim
112 words
A logic level translator having high switching speeds for converting ECL logic levels into TTL logic levels, said translator comprising: input means for receiving ECL input logic level signals; output means formed of an output transistor being adapted to provide TTL output logic level signals; current mirror means interconnected between said input means and said output means for turning on and off said output transistor; and circuit means for increasing transient response of said current mirror means so as to facilitate turning on and off quickly said output transistor whereby the TTL output logic levels have a relatively small propagation delay in response to transitions of the ECL input logic level signals.
Claim 13
Dependent Claim
37 words
A logic level translator as claimed in Claim 10, wherein said transient means includes a first high-pass network formed of a resistor and a capacitor and a second high-pass network formed of a resistor and a capacitor.
Claim 14
Dependent Claim
17 words
A logic level translator as claimed in Claim 10, wherein said output transistor comprises a Schottky transistor.
Claim 15
Dependent Claim
33 words
A logic level translator as claimed in Claim 10, wherein the ECL input logic signals are +5 volts representing the logic level "1" and 5 volts minus 750mv representing the logic level "0".
Claim 16
Dependent Claim
32 words
A logic level translator as claimed in Claim 10, wherein the TTL output logic level signals are +5 volts representing the logic level "1" and 0.25 volts representing the logic level "0".
Claim 17
Dependent Claim
24 words
A logic level translator as claimed in Claim 10, wherein said translator is formed on a single silicon chip of a semiconductor integrated circuit.
Claim 18
Dependent Claim
269 words
A logic level translator having high switching speeds for converting ECL logic levels to TTL logic levels, said translator comprising: a first and second input transistors having their collectors connected to a supply potential, the bases of said first and second transistors being adapted to receive ECL input logic level signals: a current mirror formed of a pair of third and fourth transistors having their emitters connected together and to a ground potential; a first resistor and a first capacitor being connected in parallel with its one end connected to the emitter of said first transistor and its other end connected to the collector of said third transistor; a second resistor and a second capacitor being connected in parallel with its one end connected to the emitter of said second transistor and its other end connected to the collector of said fourth transistor; an inverter transistor having its base connected to the collector of said fourth transistor, its collector connected to the supply potential via a load resistor, and its emitter connected to the ground potential; circuit means for generating large transient drive current differences at the bases of said third and fourth transistors so as to facilitate turning on quickly one of said third and fourth transistors and turning off quickly the other one of said third and fourth transistors; and said base of said inverter transistor being responsive to said transient drive current differences at the bases of said third and fourth transistors so as to create a very fast output response at TTL logic levels on its collector during transitions of the ECL input logic levels.
Claim 19
Dependent Claim
269 words
A logic level translator having high switching speeds for converting ECL logic levels to TTL logic levels, said translator comprising: a first and second input transistors having their collectors connected to a supply potential, the bases of said first and second transistors being adapted to receive ECL input logic level signals: a current mirror formed of a pair of third and fourth transistors having their emitters connected together and to a ground potential; a first resistor and a first capacitor being connected in parallel with its one end connected to the emitter of said first transistor and its other end connected to the collector of said third transistor; a second resistor and a second capacitor being connected in parallel with its one end connected to the emitter of said second transistor and its other end connected to the collector of said fourth transistor; an inverter transistor having its base connected to the collector of said fourth transistor, its collector connected to the supply potential via a load resistor, and its emitter connected to the ground potential; circuit means for generating large transient drive current differences at the bases of said third and fourth transistors so as to facilitate turning on quickly one of said third and fourth transistors and turning off quickly the other one of said third and fourth transistors; and said base of said inverter transistor being responsive to said transient drive current differences at the bases of said third and fourth transistors so as to create a very fast output response at TTL logic levels on its collector during transitions of the ECL input logic levels.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.