EP0203475A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Integrated circuit RF amplifier module
Assignee: Ericsson Inc
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Filing: 1986-05-15
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Granted: —
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Expires: 2006-05-15
Abstract
Abstract A four-terminal integrated circuit high-frequency RF amplifier connects to external circuitry via a ground terminal, an RF input terminal, an RF output terminal and a DC biasing terminal. A two stage amplification architecture is employed - a current gain transistor (common-emitter) is cascoded with a subsequent voltage gain transistor (common-base) while yet maintaining RF signal inversion overall from input to output so as to increase stability. A biasing current-mirror transistor provides biasing current to the current-gain transistor. A fourth transistor connected as a forward-biased collector-base shorted diode between the current mirror biasing transistor and a common external biasing terminal supplies bias current to the current-mirror biasing transistor while simultaneously minimizing voltage swings across the current-gain transistor. The amplifier module has very low input capacitance which does not change appreciably with changes in load impedance, and operates with great stability under a wide range of different input and output conditions and RF frequencies. Because of its relative simplicity and compactness, the amplifier can be used to great advantage as an IC "building block" in a variety of different applications.
Inventors
- 👤 Richard John Patch
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 22:14
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/189; H03F3/19; H03F1/00; H03F1/08; H03F1/22
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
325 words
A monolithic integrated circuit amplifier module requiring only four external electrical connections and comprising: an input signal terminal; an output signal terminal; a DC bias input terminal; a current-gain transistor amplifier connected to said input signal terminal and to said ground terminal; a voltage-gain transistor amplifier connected in cascode with said current-gain amplifier and to said output signal terminal; said cascoded amplifiers being connected to collectively provide an output from the module which is inverted or approximately 180° out-of-phase with respect to an input signal to the module; DC biasing means connected to said DC bias input terminal and to each of said transistor amplifiers for establishing DC bias currents within each of said transistor amplifiers; said current-gain transistor amplifier including a common-emitter connected first transistor; said voltage-gain transistor amplifier including a common-base connected second transistor having an emitter electrode connected to a collector electrode of said first transistor; each of said transistors being a bipolar NPN transistor and each of said cascoded amplifiers consisting of only a single transistor structure; and said DC biasing means including a first bias transistor (also a bipolar NPN transistor) connected in a current mirror arrangement with said common-emitter first transistor to establish a DC bias current therein which is multiplied by a factor M when compared to DC current flowing in the first bias transistor; a second bias transistor (also a bipolar NPN transistor) connected in a shorted base-collector diode arrangement with said DC bias input terminal and said first bias transistor so as to supply DC bias current thereto and to minimize the voltage swing across the current-gain transistor amplifier; first resistance connected in series between said first and second bias transistors; second resistance connected in series between the base of said common-emitter first transistor and the collector of said first bias transistor; and third resistance of value approximately M times said second resistance, connected in series between the base and collector of said second bias transistor.
Claim 2
Dependent Claim
325 words
A monolithic integrated circuit amplifier module requiring only four external electrical connections and comprising: an input signal terminal; an output signal terminal; a DC bias input terminal; a current-gain transistor amplifier connected to said input signal terminal and to said ground terminal; a voltage-gain transistor amplifier connected in cascode with said current-gain amplifier and to said output signal terminal; said cascoded amplifiers being connected to collectively provide an output from the module which is inverted or approximately 180° out-of-phase with respect to an input signal to the module; DC biasing means connected to said DC bias input terminal and to each of said transistor amplifiers for establishing DC bias currents within each of said transistor amplifiers; said current-gain transistor amplifier including a common-emitter connected first transistor; said voltage-gain transistor amplifier including a common-base connected second transistor having an emitter electrode connected to a collector electrode of said first transistor; each of said transistors being a bipolar NPN transistor and each of said cascoded amplifiers consisting of only a single transistor structure; and said DC biasing means including a first bias transistor (also a bipolar NPN transistor) connected in a current mirror arrangement with said common-emitter first transistor to establish a DC bias current therein which is multiplied by a factor M when compared to DC current flowing in the first bias transistor; a second bias transistor (also a bipolar NPN transistor) connected in a shorted base-collector diode arrangement with said DC bias input terminal and said first bias transistor so as to supply DC bias current thereto and to minimize the voltage swing across the current-gain transistor amplifier; first resistance connected in series between said first and second bias transistors; second resistance connected in series between the base of said common-emitter first transistor and the collector of said first bias transistor; and third resistance of value approximately M times said second resistance, connected in series between the base and collector of said second bias transistor.
Claim 3
Dependent Claim
139 words
An ac signal amplifier comprising: an input signal terminal; an output signal terminal; a DC bias input terminal; a ground reference terminal; first and second transistors connected in a current mirror configuration with the first transistor being coupled to said DC bias terminal to establish a DC bias current through the second transistor and with the second transistor being coupled to said input signal terminal and adapted to provide current-gain amplification of input signals received therefrom; and a further transistor also coupled to said DC bias terminal to establish a DC bias current therethrough and said further transistor being connected in cascode with said second transistor to provide voltage-gain amplification of the current-gain amplified signals supplied thereto through the second transistor, said further transistor being connected to provide current and voltage gain amplified output signals to said output terminal.
Claim 4
Dependent Claim
139 words
An ac signal amplifier comprising: an input signal terminal; an output signal terminal; a DC bias input terminal; a ground reference terminal; first and second transistors connected in a current mirror configuration with the first transistor being coupled to said DC bias terminal to establish a DC bias current through the second transistor and with the second transistor being coupled to said input signal terminal and adapted to provide current-gain amplification of input signals received therefrom; and a further transistor also coupled to said DC bias terminal to establish a DC bias current therethrough and said further transistor being connected in cascode with said second transistor to provide voltage-gain amplification of the current-gain amplified signals supplied thereto through the second transistor, said further transistor being connected to provide current and voltage gain amplified output signals to said output terminal.
Claim 5
Dependent Claim
25 words
An amplifier as in claim 2 wherein a forward-biased diode structure and a series resistance couple said DC bias input terminal to said first transistor.
Claim 6
Dependent Claim
15 words
An amplifier as in claim 3 wherein said diode structure comprises a base-collector connected transistor.
Claim 7
Dependent Claim
24 words
An amplifier as in claim 2 wherein each of said transistors is a bipolar NPN transistor fabricated within the same monolithic integrated circuit wafer.
Claim 8
Dependent Claim
24 words
An amplifier as in claim 4 wherein each of said transistors is a bipolar NPN transistor fabricated within the same monolithic integrated circuit wafer.
Claim 9
Dependent Claim
192 words
An amplifier comprising: an input signal terminal; an output signal terminal; a DC bias input terminal; a ground reference terminal; first and second transistors connected in a current mirror configuration with the first transistor being coupled to said DC bias terminal to establish a DC bias current through the second transistor and with the second transistor being coupled to said input signal terminal and adapted to provide current-gain amplification of input signals received therefrom; a further transistor also coupled to said DC bias terminal to establish a DC bias current therethrough and said further transistor being connected in cascode with said second transistor to provide voltage-gain amplification of the current-gain amplified signals supplied thereto through the second transistor, said further transistor being connected to provide current and voltage gain amplified output signals to said output signal terminal; each of said transistors being a bipolar NPN transistor fabricated within the same monolithic integrated circuit wafer; and wherein said integrated circuit wafer includes at least one electrical connection pad to serve as each of said terminals and wherein at least one of said terminals comprises a plurality of such pads electrically connected in parallel.
Claim 10
Dependent Claim
192 words
An amplifier comprising: an input signal terminal; an output signal terminal; a DC bias input terminal; a ground reference terminal; first and second transistors connected in a current mirror configuration with the first transistor being coupled to said DC bias terminal to establish a DC bias current through the second transistor and with the second transistor being coupled to said input signal terminal and adapted to provide current-gain amplification of input signals received therefrom; a further transistor also coupled to said DC bias terminal to establish a DC bias current therethrough and said further transistor being connected in cascode with said second transistor to provide voltage-gain amplification of the current-gain amplified signals supplied thereto through the second transistor, said further transistor being connected to provide current and voltage gain amplified output signals to said output signal terminal; each of said transistors being a bipolar NPN transistor fabricated within the same monolithic integrated circuit wafer; and wherein said integrated circuit wafer includes at least one electrical connection pad to serve as each of said terminals and wherein at least one of said terminals comprises a plurality of such pads electrically connected in parallel.
Claim 11
Dependent Claim
22 words
An RF amplifier as in claim 7, wherein said ground reference terminal comprises a plurality of said pads electrically connected in parallel.
Claim 12
Dependent Claim
23 words
An RF amplifier as in claim 8, wherein said DC bias input terminal comprises a plurality of said pads electrically connected in parallel.
Claim 13
Dependent Claim
178 words
An amplifier comprising: an input signal terminal; an output signal terminal; a DC bias input terminal; a ground reference terminal; first and second transistors connected in a current mirror configuration with the first transistor being, coupled to said DC bias terminal to establish a DC bias current through the second transistor and with the second transistor being coupled to said input signal terminal and adapted to provide current-gain amplification of input signals received therefrom; a further transistor also coupled to said DC bias terminal to establish a DC bias current therethrough and said further transistor being connected in cascode with said second transistor to provide voltage-gain amplification of the current-gain amplified signals supplied thereto through the second transistor, said further transistor being connected to provide current and voltage gain amplified output signals to said output signal terminal; wherein said second transistor has a signal input which also receives a DC bias established by the first transistor and further comprising a decoupling resistance connected between said signal input of said second transistor and the DC bias establishing first transistor.
Claim 14
Dependent Claim
178 words
An amplifier comprising: an input signal terminal; an output signal terminal; a DC bias input terminal; a ground reference terminal; first and second transistors connected in a current mirror configuration with the first transistor being, coupled to said DC bias terminal to establish a DC bias current through the second transistor and with the second transistor being coupled to said input signal terminal and adapted to provide current-gain amplification of input signals received therefrom; a further transistor also coupled to said DC bias terminal to establish a DC bias current therethrough and said further transistor being connected in cascode with said second transistor to provide voltage-gain amplification of the current-gain amplified signals supplied thereto through the second transistor, said further transistor being connected to provide current and voltage gain amplified output signals to said output signal terminal; wherein said second transistor has a signal input which also receives a DC bias established by the first transistor and further comprising a decoupling resistance connected between said signal input of said second transistor and the DC bias establishing first transistor.
Claim 15
Dependent Claim
68 words
An RF amplifier as in claim 10 wherein said first and second transistors have geometrically scaled structures to establish current multiplication ratio I:M therebetween and further comprising a matching resistance included within said current mirror configuration, the ratio between said decoupling and matching resistances being M:1 so as to maintain the 1:M DC current ratio between said first and second transistors in the presence of said decoupling resistance.
Claim 16
Dependent Claim
37 words
An RF amplifier as in claim 2, 3, 4 or 5 wherein said cascoded second and further transistors collectively provide an RF output which is inverted or approximately 180° out of phase with an RF input signal.
Claim 17
Dependent Claim
242 words
A monolithic integrated circuit RF amplifier for amplifying signals in excess of 100 MHz, said amplifier being fabricated from a P-type semiconductor substrate starting material and comprising: a voltage RF amplifying transistor for producing an RF voltage across an output thereof proportional to an input RF current applied in series with said output; a single current RF amplifier transistor having only a single transistor amplifier stage with an output operatively coupled in series with the output of the voltage amplifier transistor and connected to current gain amplify an input RF signal thereto, for controlling the current applied to said voltage amplifier transistor in response to the input RF signal thereby providing a current and voltage gain amplified RF signal across the collective series-connected outputs of said amplifying transistors having a frequency in excess of 100 MHz; and biasing means connected to each of said amplifying transistors and to a common DC bias input for establishing quiescent biasing current within each of the voltage and current amplifying transistors which is substantially independent of signal level, said biasing means includes at least a first transistor; said current RF amplifying transistor is connected in a current mirror configuration with said first transistor; and said biasing means further includes at least one diode connected in series with said first transistor to supply bias current thereto and including a resistor connecting the current RF transistor amplifier to the series-connected junction of said diode and said first transistor.
Claim 18
Dependent Claim
242 words
A monolithic integrated circuit RF amplifier for amplifying signals in excess of 100 MHz, said amplifier being fabricated from a P-type semiconductor substrate starting material and comprising: a voltage RF amplifying transistor for producing an RF voltage across an output thereof proportional to an input RF current applied in series with said output; a single current RF amplifier transistor having only a single transistor amplifier stage with an output operatively coupled in series with the output of the voltage amplifier transistor and connected to current gain amplify an input RF signal thereto, for controlling the current applied to said voltage amplifier transistor in response to the input RF signal thereby providing a current and voltage gain amplified RF signal across the collective series-connected outputs of said amplifying transistors having a frequency in excess of 100 MHz; and biasing means connected to each of said amplifying transistors and to a common DC bias input for establishing quiescent biasing current within each of the voltage and current amplifying transistors which is substantially independent of signal level, said biasing means includes at least a first transistor; said current RF amplifying transistor is connected in a current mirror configuration with said first transistor; and said biasing means further includes at least one diode connected in series with said first transistor to supply bias current thereto and including a resistor connecting the current RF transistor amplifier to the series-connected junction of said diode and said first transistor.
Claim 19
Dependent Claim
261 words
An integrated circuit amplifier comprising: an input signal terminal (B); a ground terminal (A); a first transistor (Q1) including a base, a collector and an emitter, the base being coupled to the collector and to said input signal terminal (B), and the emitter being coupled to said ground terminal (A); a second transistor (Q2) including a base, a collector and an emitter, the emitter being coupled to said ground terminal (A), and the base being coupled to the base of said first transistor (Q2); a bias input terminal (D); a diode (Q3) including anode and cathode electrodes, one electrode being coupled to said biasing terminal (D), and the other electrode being coupled to the collector of said first transistor (2 1 ) ; an output signal terminal (C); a further transistor (Q4) including a base, a collector and an emitter, the collector being coupled to said output signal terminal (C), the base being coupled to said bias input terminal (D), and the emitter being coupled to the collector of said second transistor (Q2); the size of the emitter of said second transistor (Q2) being a predetermined multiple of the size of the emitter of said first transistor (Ql); a first resistance (Rl) connected between the collector of said first transistor (Q1) and the base of said second transistor (Q2); and a second resistance (R2) connected between the base of said first transistor (Q1) and the collector of said first transistor (Q1), wherein the value of said second resistance is larger by said predetermined multiple than the value of said first resistance.
Claim 20
Dependent Claim
261 words
An integrated circuit amplifier comprising: an input signal terminal (B); a ground terminal (A); a first transistor (Q1) including a base, a collector and an emitter, the base being coupled to the collector and to said input signal terminal (B), and the emitter being coupled to said ground terminal (A); a second transistor (Q2) including a base, a collector and an emitter, the emitter being coupled to said ground terminal (A), and the base being coupled to the base of said first transistor (Q2); a bias input terminal (D); a diode (Q3) including anode and cathode electrodes, one electrode being coupled to said biasing terminal (D), and the other electrode being coupled to the collector of said first transistor (2 1 ) ; an output signal terminal (C); a further transistor (Q4) including a base, a collector and an emitter, the collector being coupled to said output signal terminal (C), the base being coupled to said bias input terminal (D), and the emitter being coupled to the collector of said second transistor (Q2); the size of the emitter of said second transistor (Q2) being a predetermined multiple of the size of the emitter of said first transistor (Ql); a first resistance (Rl) connected between the collector of said first transistor (Q1) and the base of said second transistor (Q2); and a second resistance (R2) connected between the base of said first transistor (Q1) and the collector of said first transistor (Q1), wherein the value of said second resistance is larger by said predetermined multiple than the value of said first resistance.
Claim 21
Dependent Claim
213 words
An integrated circuit amplifier comprising: an input signal terminal (B); a ground terminal (A); a first transistor (Q1) including a base, a collector and an emitter, the base being coupled to the collector and to said input signal terminal (B), and the emitter being coupled to said ground terminal (A); a second transistor (Q2) including a base, a collector and an emitter, the emitter being coupled to said ground terminal (A), and the base being coupled to the base of said first transistor (Q2); a bias input terminal (D); a diode (Q3) including anode and cathode electrodes, one electrode being coupled to said biasing terminal (D), and the other electrode being coupled to the collector of said first transistor (Ql); an output signal terminal (C); a further transistor (Q4) including a base, a collector and an emitter, the collector being coupled to said output signal terminal (C), the base being coupled to said bias input terminal (D), and the emitter being coupled to the collector of said second transistor (Q2); a first resistance (Rl) connected between the collector of said first transistor (Ql) and the base of said second transistor (Q2); and a second resistance (R2) connected between the base of said first transistor (Ql) and the collector of said first transistor (Ql).
Claim 22
Dependent Claim
213 words
An integrated circuit amplifier comprising: an input signal terminal (B); a ground terminal (A); a first transistor (Q1) including a base, a collector and an emitter, the base being coupled to the collector and to said input signal terminal (B), and the emitter being coupled to said ground terminal (A); a second transistor (Q2) including a base, a collector and an emitter, the emitter being coupled to said ground terminal (A), and the base being coupled to the base of said first transistor (Q2); a bias input terminal (D); a diode (Q3) including anode and cathode electrodes, one electrode being coupled to said biasing terminal (D), and the other electrode being coupled to the collector of said first transistor (Ql); an output signal terminal (C); a further transistor (Q4) including a base, a collector and an emitter, the collector being coupled to said output signal terminal (C), the base being coupled to said bias input terminal (D), and the emitter being coupled to the collector of said second transistor (Q2); a first resistance (Rl) connected between the collector of said first transistor (Ql) and the base of said second transistor (Q2); and a second resistance (R2) connected between the base of said first transistor (Ql) and the collector of said first transistor (Ql).
Claim 23
Dependent Claim
189 words
An integrated circuit amplifier comprising: an input signal terminal (B); a ground terminal (A); a first transistor (Q1) including a base, a collector and an emitter, the base being coupled to the collector and to said input signal terminal (B), and the emitter being coupled to said ground terminal (A); a second transistor (Q2) including a base, a collector and an emitter, the emitter being coupled to said ground terminal (A), and the base being coupled to the base of said first transistor (Q2); a bias input terminal (D); a diode (Q3) including anode and cathode electrodes, one electrode being coupled to said biasing terminal (D), and the other electrode being coupled to the collector of said first transistor (Ql); an output signal terminal (C); a further transistor (Q4) including a base, a collector and an emitter, the collector being coupled to said output signal terminal (C), the base being coupled to said bias input terminal (D), and the emitter being coupled to the collector of said second transistor (Q2); resistance means for coupling the said other electrode of said diode to the collector of said first transistor (Ql).
Claim 24
Dependent Claim
189 words
An integrated circuit amplifier comprising: an input signal terminal (B); a ground terminal (A); a first transistor (Q1) including a base, a collector and an emitter, the base being coupled to the collector and to said input signal terminal (B), and the emitter being coupled to said ground terminal (A); a second transistor (Q2) including a base, a collector and an emitter, the emitter being coupled to said ground terminal (A), and the base being coupled to the base of said first transistor (Q2); a bias input terminal (D); a diode (Q3) including anode and cathode electrodes, one electrode being coupled to said biasing terminal (D), and the other electrode being coupled to the collector of said first transistor (Ql); an output signal terminal (C); a further transistor (Q4) including a base, a collector and an emitter, the collector being coupled to said output signal terminal (C), the base being coupled to said bias input terminal (D), and the emitter being coupled to the collector of said second transistor (Q2); resistance means for coupling the said other electrode of said diode to the collector of said first transistor (Ql).
Claim 25
Dependent Claim
210 words
An integrated circuit amplifier comprising: an input signal terminal (B); a ground terminal (A); a first transistor (Ql) including a base, a collector and an emitter, the base being coupled to the collector and to said input signal terminal (B), and the emitter being coupled to said ground terminal (A); a second transistor (Q2) including a base, a collector and an emitter, the emitter being coupled to said ground terminal (A), and the base being coupled to the base of said first transistor (Q2); a bias input terminal (D); a diode (Q3) including anode and cathode electrodes, one electrode being coupled to said biasing terminal (D). and the other electrode being coupled to the collector of said first transistor (81); an output signal terminal (C); a further transistor (Q4) including a base, a collector and an emitter, the collector being coupled to said output signal terminal (C), the base being coupled to said bias input terminal (D), and the emitter being coupled to the collector of said second transistor (Q2); bypass capacitor means, connected externally between said biasing terminal (D) and ground potential, for maintaining said biasing terminal at ground potential with respect to signal frequencies; and external means for applying a DC biasing current to said biasing terminal (D).
Claim 26
Dependent Claim
210 words
An integrated circuit amplifier comprising: an input signal terminal (B); a ground terminal (A); a first transistor (Ql) including a base, a collector and an emitter, the base being coupled to the collector and to said input signal terminal (B), and the emitter being coupled to said ground terminal (A); a second transistor (Q2) including a base, a collector and an emitter, the emitter being coupled to said ground terminal (A), and the base being coupled to the base of said first transistor (Q2); a bias input terminal (D); a diode (Q3) including anode and cathode electrodes, one electrode being coupled to said biasing terminal (D). and the other electrode being coupled to the collector of said first transistor (81); an output signal terminal (C); a further transistor (Q4) including a base, a collector and an emitter, the collector being coupled to said output signal terminal (C), the base being coupled to said bias input terminal (D), and the emitter being coupled to the collector of said second transistor (Q2); bypass capacitor means, connected externally between said biasing terminal (D) and ground potential, for maintaining said biasing terminal at ground potential with respect to signal frequencies; and external means for applying a DC biasing current to said biasing terminal (D).
Claim 27
Dependent Claim
114 words
A monolithic integrated circuit amplifier comprising: signal input and signal output terminals; a DC bias input terminal; two cascoded signal amplifying transistors including a current-gain stage transistor feeding a voltage-gain stage transistor, said cascoded transistors collectively providing signal inversion as well as current and voltage gain between said signal input and signal output terminals; and common DC bias control means connected to said bias input terminal and to said transistors to simultaneously control DC bias quiescent operating points for both said transistors; said common DC bias control means including a current-mirror transistor connected in current-mirror relationship with the current-gain stage transistor; and a forward-biased diode and resistance connected in series with said current-mirror transistor.
Claim 28
Dependent Claim
114 words
A monolithic integrated circuit amplifier comprising: signal input and signal output terminals; a DC bias input terminal; two cascoded signal amplifying transistors including a current-gain stage transistor feeding a voltage-gain stage transistor, said cascoded transistors collectively providing signal inversion as well as current and voltage gain between said signal input and signal output terminals; and common DC bias control means connected to said bias input terminal and to said transistors to simultaneously control DC bias quiescent operating points for both said transistors; said common DC bias control means including a current-mirror transistor connected in current-mirror relationship with the current-gain stage transistor; and a forward-biased diode and resistance connected in series with said current-mirror transistor.
Claim 29
Dependent Claim
42 words
A monolithic integrated circuit RF amplifier as in claim 18 further comprising: decoupling resistance connected in series between said current-mirror transistor and said current-gain stage transistor to increase the input impedance of the RF input terminal otherwise lowered by said forward-biased diode.
Claim 30
Dependent Claim
32 words
A monolithic integrated circuit RF amplifier as in claim 18 or 19 wherein said amplifier is packaged within a four leaded Micro-X integrated circuit package providing only four external electrical connection points.
Claim 31
Dependent Claim
218 words
An amplifier comprising: an input signal terminal; an output signal terminal; a DC bias input terminal; a ground reference terminal; first and second transistors connected in a current mirror configuration with the first transistor being coupled to said DC bias terminal to establish a DC bias current through the second transistor and with the second transistor being coupled to said input signal terminal and adapted to provide current-gain amplification of input signals received therefrom; a further transistor also coupled to said DC bias terminal to establish a DC bias current therethrough and said further transistor being connected in cascode with said second transistor to provide voltage-gain amplification of the current-gain amplified signals supplied thereto through the second transistor, said further transistor being connected to provide current and voltage gain amplified output signals to said output signal terminal; a forward-biased diode structure and a series resistance coupling said DC bias input terminal to said first transistor; said diode structure including a base-collector connected transistor; each of said transistors being a bipolar NPN transistor fabricated within the same monolithic integrated circuit wafer; and wherein said integrated circuit wafer includes at least one electrical connection pad to serve as each of said terminals and wherein at least one of said terminals comprises a plurality of such pads electrically connected in parallel.
Claim 32
Dependent Claim
218 words
An amplifier comprising: an input signal terminal; an output signal terminal; a DC bias input terminal; a ground reference terminal; first and second transistors connected in a current mirror configuration with the first transistor being coupled to said DC bias terminal to establish a DC bias current through the second transistor and with the second transistor being coupled to said input signal terminal and adapted to provide current-gain amplification of input signals received therefrom; a further transistor also coupled to said DC bias terminal to establish a DC bias current therethrough and said further transistor being connected in cascode with said second transistor to provide voltage-gain amplification of the current-gain amplified signals supplied thereto through the second transistor, said further transistor being connected to provide current and voltage gain amplified output signals to said output signal terminal; a forward-biased diode structure and a series resistance coupling said DC bias input terminal to said first transistor; said diode structure including a base-collector connected transistor; each of said transistors being a bipolar NPN transistor fabricated within the same monolithic integrated circuit wafer; and wherein said integrated circuit wafer includes at least one electrical connection pad to serve as each of said terminals and wherein at least one of said terminals comprises a plurality of such pads electrically connected in parallel.
Claim 33
Dependent Claim
196 words
A monolithic integrated circuit amplifier comprising: signal input and signal output terminals; a DC bias input terminal; two cascoded signal amplifying transistors including a current-gain stage transistor feeding a voltage-gain stage transistor, said cascoded transistors collectively providing signal inversion as well as current and voltage gain between said signal input and signal output terminals; and common DC bias control means connected to said bias input terminal and to said transistors to simultaneously control DC bias quiescent operating points for both said transistors; wherein said amplifier is packaged within a four leaded Micro-X integrated circuit package providing only four external electrical connection points, and said bias control means includes a predetermined decoupling resistance network means connection to at least one of said transistors, which network acts to decouple the bias control means from the signal being amplified. 23. A monolithic integrated circuit ac signal amplifier module as in claim 22 wherein said bias control means includes a current mirror bias transistor and said resistance network means comprises a pair of resistances having predetermined scaled resistance values corresponding to the current mirror ratio established between said current mirror bias transistor and said at least one of said transistors.
Claim 34
Dependent Claim
118 words
A monolithic integrated circuit ac signal amplifier module comprising: signal input and output terminals; a DC bias input terminal; two cascoded signal amplifying transistors including a current-gain stage transistor feeding a voltage-gain stage transistor, said cascoded transistors collectively providing signal inversion as well as current and voltage gain between said signal input and output terminals; and common DC bias control means connected to said bias input terminal and to said transistors to simultaneously control DC bias quiescent operating points for both said transistors, wherein said module includes at least one electrical connection pad to serve as each of said terminals and wherein at least one of said terminals comprises a plurality of such pads electrically connected in parallel.
Claim 35
Dependent Claim
118 words
A monolithic integrated circuit ac signal amplifier module comprising: signal input and output terminals; a DC bias input terminal; two cascoded signal amplifying transistors including a current-gain stage transistor feeding a voltage-gain stage transistor, said cascoded transistors collectively providing signal inversion as well as current and voltage gain between said signal input and output terminals; and common DC bias control means connected to said bias input terminal and to said transistors to simultaneously control DC bias quiescent operating points for both said transistors, wherein said module includes at least one electrical connection pad to serve as each of said terminals and wherein at least one of said terminals comprises a plurality of such pads electrically connected in parallel.
Claim 36
Dependent Claim
117 words
A monolithic integrated circuit ac signal amplifier module comprising: signal input and output terminals; a DC bias input terminal; two cascoded signal amplifying transistors including a current-gain stage transistor feeding a voltage-gain stage transistor, said cascoded transistors collectively providing signal inversion as well as current and voltage gain between said signal input and output terminals; common DC bias control means connected to said bias input terminal and to said transistors to simultaneously control DC bias quiescent operating points for both said transistors; by pass capacitor means, connected externally between said biasing terminal and ground potential, for maintaining said biasing terminal at signal ground potential; and external means for applying a DC biasing current to said biasing terminal.
Claim 37
Dependent Claim
117 words
A monolithic integrated circuit ac signal amplifier module comprising: signal input and output terminals; a DC bias input terminal; two cascoded signal amplifying transistors including a current-gain stage transistor feeding a voltage-gain stage transistor, said cascoded transistors collectively providing signal inversion as well as current and voltage gain between said signal input and output terminals; common DC bias control means connected to said bias input terminal and to said transistors to simultaneously control DC bias quiescent operating points for both said transistors; by pass capacitor means, connected externally between said biasing terminal and ground potential, for maintaining said biasing terminal at signal ground potential; and external means for applying a DC biasing current to said biasing terminal.
References Cited (Backward Citations)
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