Apparatus for storing digital data words

Claim 2

Apparatus for storing and retrieving digital data words and including data storage equipment adapted for storing each said data word on a mechanically-driven medium, said apparatus being characterised in that it comprises error correction means adapted for correcting errors in retrieved data words, which error correction means comprise: error correction circuitry adapted to generate error correction bits for said data words, and correction bit storage equipment adapted for storing said correction bits independently from said data word on a mechanically driven medium, said error correction circuitry being arranged operatively to correct errors in retrieved said data words using said error correction bits.

Claim 3

Apparatus according to Claim 1, further characterised in that said data storage equipment comprises data storage units arranged for operatively respectively storing different portions of each said data word, and said correction bit storage equipment comprises at least one correction bit storage unit.

Claim 4

Apparatus according to Claim 2, further characterised in that said error correction circuitry is arranged operatively to correct said data words in a manner that permits the failure of any single said storage unit.

Claim 5

Apparatus according to Claim 2, further characterised in that there are a plurality of correction bit storage units, and various said error correction bits are arranged operatively to be stored in different said correction bit storage units.

Claim 6

Apparatus according to Claim 2, further characterised in that no two said error correction bits for a given said data word are stored in a single said correction bit storage unit.

Claim 7

Apparatus according to Claim 2, further characterised in that said error correction circuitry comprises: an error correction unit arranged operatively to generate a set of said error correction bits for fewer than all of the bits in each said data word at a time, and routing circuitry adapted for routing the bits of said data word in successive groups to said error correction unit to generate a plurality of sets of said error correction bits.

Claim 8

Apparatus according to Claim 2, further characterised in that said error correction circuitry comprises: a plurality of error correction units each of which is arranged operatively to generate a set of error correction bits for a group of fewer than all of the bits in each said data word, and routing circuitry adapted for routing groups of the bits in each said data word in parallel to said error correction units to generate a plurality of sets of said data bits..

Claim 9

Apparatus according to Claims 6 or 7, wherein each said data word has 64 bits, and being further characterised in that each said error correction unit is arranged operatively to generate seven error correction bits for each group of 32 bits of each said data word.

Claim 10

Apparatus according to any of Claims 2 to 8, wherein said data words are delivered in succession via a parallel data bus for storage and retrieval, said system being further characterised in comprising an adaptor connected between said bus and said storage units and adapted for routing data words between said bus and said storage units.

Claim 11

Apparatus for storing digital data words and adapted for delivering them in succession to a parallel data bus when requested by a data processor connected to said bus, said apparatus being characterised in comprising: storage units each having a mechanically-driven medium, and a head for reading said medium, the storage units being so arranged that different portions of each said data word are stored in different said storage units, one said storage unit having associated therewith a first delay time between when a particular said data word is requested and when the portion of said particular data word stored in said storage unit is ready to be delivered to said bus, another said storage unit having associated therewith a second delay time, different from said first delay time, between when said particular data word is requested and when the portion of said data word stored in said other storage unit is ready to be delivered to said bus; and an adaptor arranged for operative connection between said bus and said storage units and adapted to respond to said request from said data processor by causing said storage units to read said portions of each successive said word from said storage units.

Claim 12

Apparatus for storing digital data words and adapted for delivering them in succession to a parallel data bus when requested by a data processor connected to said bus, said apparatus being characterised in comprising: storage units each having a mechanically-driven medium, and a head for reading said medium, the storage units being so arranged that different portions of each said data word are stored in different said storage units, one said storage unit having associated therewith a first delay time between when a particular said data word is requested and when the portion of said particular data word stored in said storage unit is ready to be delivered to said bus, another said storage unit having associated therewith a second delay time, different from said first delay time, between when said particular data word is requested and when the portion of said data word stored in said other storage unit is ready to be delivered to said bus; and an adaptor arranged for operative connection between said bus and said storage units and adapted to respond to said request from said data processor by causing said storage units to read said portions of each successive said word from said storage units.

Claim 13

Apparatus according to Claim 10, further characterised in that said adaptor is further adapted in operation to delay the delivery of any of said portions to said bus until all said portions are ready to be delivered.

Claim 14

Apparatus according to Claim 9 or Claim 10, further characterised in that an individual bus is provided between each said storage unit and said adaptor; in that each said storage unit is operatively arranged to send a drain command over its corresponding individual bus to said adaptor when said portion of said data stored in said storage unit is ready to be delivered; and in that said adaptor is operatively arranged to monitor the appearances of said drain commands on all of said individual buses, and, when said drain commands from all said storage units have appeared, to drain all said portions of said data word from said storage units and to deliver them simultaneously to said parallel data bus.

Claim 15

Apparatus according to Claim 10, further characterised in that said adaptor is arranged operatively to generate parallel error correction bits for each said data word, the apparatus being further arranged such that at least one of said error correction bits is stored on a storage unit that does not hold any said portion of the data word related to said error correction bits.

Claim 16

Apparatus according to Claim 13, further characterised in that said adaptor is further arranged operatively to cause said error correction bits to be read at a time corresponding to the time that the related said data word portions are read, and in that said adaptor comprises error correcting circuitry adapted for correcting bit errors in said data word based on said error correction bits.

Claim 17

Apparatus according to Claims 13 or 14, further characterised in being arranged such that different groups of said error correction bits are stored in different said storage units.

Claim 18

Apparatus according to Claim 15, further characterised in being arranged such that each said error correction bit for each said data word is stored in a separate said storage unit.

Claim 19

Apparatus according to any of Claims 10 to 16, further characterised in that it is arranged to store said data words when commanded by said data processor, said storage units each further comprising a head for writing on said medium, different portions of each said data word being arranged operatively to be stored in different said storage units, different said storage units having associated therewith different delay times between when a particular said word is delivered for storage and when said storage units are ready to store their respective said ' :- portions, and said adaptor being further arranged operatively to respond to said command from said data processor by delaying the delivery of any of said portions to said storage units until all said storage units are ready to store.

Claim 20

Apparatus according to Claim 17, further characterised in that each said storage unit comprises a controller having a buffer operatively arranged temporarily to hold bits that are to be written on said medium, and in that said adaptor is arranged operatively to effect the delivery of successive said data word portions to said storage units at a rate sufficient to ensure that none of the buffers in any said controller is ever empty.

Claim 21

Apparatus according to any of Claims 9 to 17, further characterised in that each said storage unit comprises a controller having a buffer operatively arranged temporarily to hold bits that have been read from said medium and are ready to be delivered, and in that said adaptor is arranged operatively to effect the delivery of successive said data word portions from said storage units at a rate sufficient to ensure that none of the buffers in any said controllers is ever full.

Claim 22

Apparatus according to any of Claims 9 to 19, further characterised in being arranged such that the portions of each said data word stored in different said storage units are equal.

Claim 23

Apparatus according to Claim 20, further characterised in that said portions are each two bits of said data word.

Claim 24

Apparatus according to any of Claims 10 to 21, further characterised in that each said individual bus conforms to the SCSI protocol.

Claim 25

Apparatus according to any of Claims 1 to 7 or 9 to 22, further characterised in that said apparatus is adapted for storing and retrieving a data word having more than 32 bits therein, and preferably 256 bits therein.

Claim 26

Apparatus according to Claims 8 or 10 or any claim appendent thereto, further characterised in being arranged such that said data words are delivered to said parallel data bus at a rate of at least 4 megabits per second per line of said bus.

Claim 27

Apparatus according to Claims 2 or 10, or any claim appendent thereto, further characterised in that each said storage unit comprises a magnetic disk drive.