Via in an integrated circuit and process for producing same

Claim 2

An improved integrated circuit structure having an interconnection of adjacent metal layers wherein a first metal layer is coated with a dielectric material and another metal layer is applied over the dielectric layer, said interconnection comprising a via electrically interconnecting at least a portion of said first metal layer with at least a portion of said second metal layer and having a first width dimension adjacent said first metal layer and an enlarged width portion adjacent said second metal layer formed by masking said dielectric with a mask having an opening conforming to said first dimension and isotropically etching a portion of the dielectric through the mask to provide said enlarged portion adjacent the upper surface of the dielectric.

Claim 3

The structure of Claim 1 wherein the dielectric separating the adjacent metal layers is planarized prior to application of the overlying metal layer to provide a more uniform upper metal layer.

Claim 4

The structure of Claim 2 wherein the planarized dielectric structure is provided by applying a first dielectric layer, planarizing the layer, and then applying a further dielectric layer followed by planarization of the subsequent dielectric layer.

Claim 5

An improved via interconnecting portions of two metal layers separated by a dielectric layer in an integrated circuit device, said via having an enlarged upper portion formed by isotropically etching an upper part of the dielectric layer and a smaller lower portion formed by anisotropically etching through the lower part of the dielectric layer.

Claim 6

An improved via interconnecting portions of two metal layers separated by a dielectric layer in an integrated circuit device, said via having an enlarged upper portion formed by isotropically etching an upper part of the dielectric layer and a smaller lower portion formed by anisotropically etching through the lower part of the dielectric layer.

Claim 7

An improved process for connecting a porticn of a first metal layer of an integrated circuit structure with a portion of an overlying second metal layer which comprises: (a) forming a dielectric layer over said first metal layer; (b) isotropically etching a first opening through an upper portion of said dielectric layer; (c) anisotropically etching through the remaining thickness of said dielectric layer below said first opening to provide a second opening of smaller width than said first opening, said second opening communicating with said portion of said first metal layer; and (d) applying a second metal layer over said dielectric layer to fill said openings and form a via to electrically connect said portion of said first metal layer with at least a portion of said second metal layer-

Claim 8

An improved process for connecting a porticn of a first metal layer of an integrated circuit structure with a portion of an overlying second metal layer which comprises: (a) forming a dielectric layer over said first metal layer; (b) isotropically etching a first opening through an upper portion of said dielectric layer; (c) anisotropically etching through the remaining thickness of said dielectric layer below said first opening to provide a second opening of smaller width than said first opening, said second opening communicating with said portion of said first metal layer; and (d) applying a second metal layer over said dielectric layer to fill said openings and form a via to electrically connect said portion of said first metal layer with at least a portion of said second metal layer-

Claim 9

The process of Claim 5 wherein said process includes the step of masking said dielectric layer with a mask having an opening therein conforming to the width of said second opening etched anisotropically in said dielectric layer.

Claim 10

The process of Claim 6 wherein the width of said mask opening is from about 1 to about 2 microns.

Claim 11

The process of Claim 6 wherein said mask opening is positioned in registry with said portion of said first metal layer to insure that said second opening subsequently anisotropically etched through said dielectric layer will only contact said underlying metal portion.

Claim 12

The process of Claim 8 which includes isotropically etching said dielectric to within about .5 micron from said underlying metal portion.

Claim 13

The process of Claim 6 wherein said isotropic etching step comprises a wet etch.

Claim 14

The process of Claim 6 wherein said isotropic etching step comprises a dry etch capable of undercutting said mask to form a first opening in the dielectric layer wider than said mask width.

Claim 15

The process of Claim 6 including the further step of planarizing said dielectric layer.

Claim 16

The process of Claim 12 wherein said step of planarizing said dielectric layer includes the steps of applying an etchable material over said dielectric layer to provide a more planar surface; etching said structure to remove an even thickness of material from the structure; and then removing the etchable material whereby high points on said underlying dielectric material will be at least partially removed.

Claim 17

The process of Claim 13 wherein said etchable material is applied in a thickness just sufficient to cover the high points of the underlying dielectric material to insure that subsequent uniform etching of a given thickness of material will remove_a maximum amount of dielectric from the high points to expedite the planarization of said dielectric-layer.

Claim 18

The process of Claim 14 wherein said etchable material is a photoresist material.

Claim 19

The process of Claim 13 wherein said step of planarization includes the further steps of applying a second layer of dielectric material over said first layer of dielectric material after planarization of said first dielectric layer; applying an etchable material over said second layer; etching said structure to remove a uniform thickness of material comprising said etchable material and high portions of said second dielectric layer; and then removing said etchable material to provide a planar surface for formation of said via therein and application of said second metal layer thereon.

Claim 20

An improved process for connecting a portion of a first metal layer of an integrated circuit structure with a portion of an overlying second metal layer which comprises: (a) forming a first dielectric layer over said first metal layer; (b) planarizing said first dielectric layer; (c) forming a second dielectric layer over said first dielectric layer; (d) planarizing said second dielectric layer; (e) masking said dielectric layer with a mask having an opening therein in registry with said portion of said first metal layer. (f) isotropically etching a first opening through an upper portion of said dielectric layer wider than said mask opening using a wet etchant said first opening extending to within about .5 micron of said underlying metal; (g) anisotropically etching through the remaining thickness of said dielectric layer below said first opening to provide a second opening of smaller width than said first opening and conforming to the opening in said mask, said second opening communicating with said portion of said first metal layer; and (h) applying a second metal layer over said-dielectric layer to fill said openings and form a via to electrically connect said portion of said first metal layer with at least a portion of said second metal layer.

Claim 21

An improved process for connecting a portion of a first metal layer of an integrated circuit structure with a portion of an overlying second metal layer which comprises: (a) forming a first dielectric layer over said first metal layer; (b) planarizing said first dielectric layer; (c) forming a second dielectric layer over said first dielectric layer; (d) planarizing said second dielectric layer; (e) masking said dielectric layer with a mask having an opening therein in registry with said portion of said first metal layer. (f) isotropically etching a first opening through an upper portion of said dielectric layer wider than said mask opening using a wet etchant said first opening extending to within about .5 micron of said underlying metal; (g) anisotropically etching through the remaining thickness of said dielectric layer below said first opening to provide a second opening of smaller width than said first opening and conforming to the opening in said mask, said second opening communicating with said portion of said first metal layer; and (h) applying a second metal layer over said-dielectric layer to fill said openings and form a via to electrically connect said portion of said first metal layer with at least a portion of said second metal layer.