CMOS memory bias systems

Claim 1

A CMOS memory bias system, where said CMOS memory is coupled to an external power supply voltage source, V CC , and is of the type including a plurality of memory cells and dummy memory cells having channels of a first conductivity type disposed in a well of a second conductivity type formed in a substrate of the first conductivity type, said system comprising: a CMOS sense amp for sensing a bit stored in said memory cell during a sense cycle; a bit line coupled to a first input of said sense amp; a dummy bit line coupled to a second input of said sense amp; at least one memory cell having gate coupling a storage capacitor to said bit line, with said storage capacitor including a storage node and a capacitor plate; means for coupling said bit line and said dummy bit line to precharge said bit line/dummy bit line pair to about V CC /2; and means for biasing said coupled bit line and dummy bit line and said capacitor plate to a multiple of V CC '

Claim 19

A system for biasing a CMOS memory array connected to an external voltage supply, V CC , with the array formed on a substrate of a first conductivity type, said array of the type having at least one sense amp for sensing a differential voltage signal, developed at first and second input nodes of the sense amp, during an externally initiated sense cycle and said array of the type having a plurality of memory cells, each cell having a storage capacitor, including a capacitor plate and a storage node, and also having a transfer gate of a first conductivity type, with the memory cells disposed in a well of a second conductivity type formed in the substrate, said system comprising: a bit line coupled to the first input node of the sense amp; a first set of memory cells controllably coupled to said bit line; a dummy bit line coupled to the second input node of said sense amp; a second set of memory cells controllably coupled to said dummy bit line; a coupling transistor, activated by clock- in g a φ BLE signal from a first state to a second state, for selectively coupling said bit line and said dummy bit line, where the magnitude of the voltage level developed on the bit line and dummy bit line after coupling is V C ; a bit line emulating voltage bias generator for generating a V BLEQ output signal; first and second biasing transistors, activated by clocking a φ BLE signal from a first state to a second state, for selectively coupling said bit line and dummy but line, respectively, to said V BLEQ signal, with said bit line emulating bias generator including circuit elements for emulating the characteristics of said sense amp, bit line, dummy bit line, coupling transistor, and biasing transistors so that the magnitude of VBLE9 is substantially equal to V C , with V BLEQ and V C equal to about V CC /2; a CP line for coupling the capacitor plates of the memory cells in said first and second sets to said V BLEQ output signal; means for biasing the well at about 1.5 V CC ; and means for clocking φ BLE and φ BLE to said second state prior to the initialization of said sense cycle.

Claim 20

A system for biasing a CMOS memory array connected to an external voltage supply, V CC , with the array formed on a substrate of a first conductivity type, said array of the type having at least one sense amp for sensing a differential voltage signal, developed at first and second input nodes of the sense amp, during an externally initiated sense cycle and said array of the type having a plurality of memory cells, each cell having a storage capacitor, including a capacitor plate and a storage node, and also having a transfer gate of a first conductivity type, with the memory cells disposed in a well of a second conductivity type formed in the substrate, said system comprising: a bit line coupled to the first input node of the sense amp; a first set of memory cells controllably coupled to said bit line; a dummy bit line coupled to the second input node of said sense amp; a second set of memory cells controllably coupled to said dummy bit line; a coupling transistor, activated by clock- in g a φ BLE signal from a first state to a second state, for selectively coupling said bit line and said dummy bit line, where the magnitude of the voltage level developed on the bit line and dummy bit line after coupling is V C ; a bit line emulating voltage bias generator for generating a V BLEQ output signal; first and second biasing transistors, activated by clocking a φ BLE signal from a first state to a second state, for selectively coupling said bit line and dummy but line, respectively, to said V BLEQ signal, with said bit line emulating bias generator including circuit elements for emulating the characteristics of said sense amp, bit line, dummy bit line, coupling transistor, and biasing transistors so that the magnitude of VBLE9 is substantially equal to V C , with V BLEQ and V C equal to about V CC /2; a CP line for coupling the capacitor plates of the memory cells in said first and second sets to said V BLEQ output signal; means for biasing the well at about 1.5 V CC ; and means for clocking φ BLE and φ BLE to said second state prior to the initialization of said sense cycle.