EP0200040A1
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EP
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Bus arbitrator
Assignee: Tektronix Inc
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Filing: 1986-04-08
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Granted: —
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Expires: 2006-04-08
Abstract
Abstract A bus arbitrator for controlling access of a master to a bus comprises a programable array logic unit for performing arbitration logic and a set of buffers for interconnecting the logic unit outputs to various lines of a control bus. The arbitrator generates bus access priority output signals which may be employed in either serial or parallel bus access priority resolution schemes and includes switch means to permit interconnection of the arbitrator in either type of scheme without circuit modification. The arbitrator asserts a common bus request output signal whenever the master requests access to the bus and retains bus access once acquired until detection of an asserted common bus request input signal. The common bus request output signal of each arbitrator accessing a bus is applied to a common bus request line which is then applied as the common bus request input to all arbitrators so that any arbitrator accessing the bus may continue to 'do so without arbitration until another arbtrator requests access. Switch means are provided to permanently assert the common bus request line so that all arbitrators must arbitrate for the bus prior to each bus access.
Inventors
- 👤 Danner Delyle
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 10:03
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
43 words
A bus arbitrator for controlling access by a master to a bus comprising: a programmable array logic circuit programmed to generate at least one output signal necessary to implement a bus arbitration system; and means to buffer said at least one output signal.
Claim 2
Dependent Claim
43 words
A bus arbitrator for controlling access by a master to a bus comprising: a programmable array logic circuit programmed to generate at least one output signal necessary to implement a bus arbitration system; and means to buffer said at least one output signal.
Claim 3
Dependent Claim
102 words
A bus arbitrator for controlling access by a master to a bus, said arbitrator comprising: means to generate a parallel priority resolution output signal, asserted when the master requests bus access, for transmittal to a priority resolving circuit when said arbitrator is used in a parallel priority resolution system; means to generate a serial priority resolution output signal, asserted when the master requests bus access and has a higher bus access priority than any other master requesting bus access in a serial priority resolution system; and means to selectively interconnect said arbitrator in either a serial or a parallel priority resolution system.
Claim 4
Dependent Claim
102 words
A bus arbitrator for controlling access by a master to a bus, said arbitrator comprising: means to generate a parallel priority resolution output signal, asserted when the master requests bus access, for transmittal to a priority resolving circuit when said arbitrator is used in a parallel priority resolution system; means to generate a serial priority resolution output signal, asserted when the master requests bus access and has a higher bus access priority than any other master requesting bus access in a serial priority resolution system; and means to selectively interconnect said arbitrator in either a serial or a parallel priority resolution system.
Claim 5
Dependent Claim
26 words
A bus arbitrator as in claim 2 wherein said means to generate said parallel and serial priority resolution output signals comprise a programmable array logic circuit.
Claim 6
Dependent Claim
85 words
A bus arbitrator for controlling access by a first master to a bus, said arbitrator comprising: a programmable array logic circuit to generate a parallel priority resolution output signal, asserted whenever said first master requests bus access, for transmittal to a priority resolving circuit when said arbitrator is used in a parallel priority resolution system; and means for generating a serial priority resolution output signal, said serial signal being asserted whenever said parallel signal is asserted while an input priority resolution signal is not asserted.
Claim 7
Dependent Claim
85 words
A bus arbitrator for controlling access by a first master to a bus, said arbitrator comprising: a programmable array logic circuit to generate a parallel priority resolution output signal, asserted whenever said first master requests bus access, for transmittal to a priority resolving circuit when said arbitrator is used in a parallel priority resolution system; and means for generating a serial priority resolution output signal, said serial signal being asserted whenever said parallel signal is asserted while an input priority resolution signal is not asserted.
Claim 8
Dependent Claim
44 words
A bus arbitrator as in claim 4 further comprising: means to continuously assert the input priority signal when said first master is to have a higher bus access priority than any other master when said arbitrator is used in a serial priority resolution system.
Claim 9
Dependent Claim
26 words
A bus arbitrator as in claim 4 further comprising: switch means to selectively connect or disconnect said serial priority resolution output signal from an external circuit.
Claim 10
Dependent Claim
27 words
A bus arbitrator as in claim 4 further comprising: switch means to selectively connect or disconnect said parallel priority resolution output signal from said priority resolving circuit.
Claim 11
Dependent Claim
80 words
A bus arbitrator as in claim 4 further comprising: means to continuously assert the input priority signal when said first master is to have a higher bus access priority than any other master when said arbitrator is used in a serial priority resolution system; switch means to selectively connect or disconnect said serial priority resolution output signal from an external circuit; and switch means to selectively connect or disconned said parallel priority resolution output signal from said priority resolving circuit.
Claim 12
Dependent Claim
16 words
A bus arbitrator for controlling access by a first master to a bus, said arbitrator comprising:
Claim 13
Dependent Claim
16 words
A bus arbitrator for controlling access by a first master to a bus, said arbitrator comprising:
Claim 14
Dependent Claim
102 words
a programmable array logic circuit programmed to assert a common bus request output signal whenever said first master requests, but does not have, access to the bus and to retain bus access once acquired until detection of an asserted common bus request input signal; and buffering means to place said common bus request output signal on a common request bus line for applying said common bus output signal as said common bus input signal to other arbitrators associated with other masters and for applying common bus output signals generated by said other arbitrators as said common bus input signal to said abritrator.
Claim 15
Dependent Claim
102 words
a programmable array logic circuit programmed to assert a common bus request output signal whenever said first master requests, but does not have, access to the bus and to retain bus access once acquired until detection of an asserted common bus request input signal; and buffering means to place said common bus request output signal on a common request bus line for applying said common bus output signal as said common bus input signal to other arbitrators associated with other masters and for applying common bus output signals generated by said other arbitrators as said common bus input signal to said abritrator.
Claim 16
Dependent Claim
33 words
A bus arbitrator as in claim 9 further comprising: switch means to selectively assert said common bus line regardless of the assertion of a common bus request output signal by said other arbitrators.
References Cited (Backward Citations)
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