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EP0199540A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Digital signal stretcher

Assignee: RCA Licensing Corp
•
Filing: 1986-04-16
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Granted: —
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Expires: 2006-04-16
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Abstract

Abstract Clocked control signals are applied from a source (20) to the input (C1) of delay means (L-1 to L-5) having a plurality of successive signal takeoff points, with the delay ( T ) between successive ones of said takeoff points being the same (e.g., a period at the signal clocking frequency, f CL ). An "and" gate (30) is provided with a plurality of inputs equal in number to the plurality of takeoff points. Each takeoff point is linked by a signal path to a respectively different one of the "and" gate inputs. A succession of two-input "or" gates (0-1 to 0-9) is provided, with one input of each "or" gate coupled to receive the output of the "and" gate (30). The last of the succession of "or" gates is coupled to a control signal output (CO). The output of each of the remainder of said succession is coupled via a respectively different one of a plurality of similar delay devices (D-1 to D-8) to the other input of the next succeeding one of said succession of "or" gates. Each of the delay devices imparts a delay (z) equal to a period at f CL . The other input of the first of said succession of "or" gates is coupled to directly receive the control signal source output.

Inventors

  • 👤 Robert Andrew Wargo

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-28 23:43
CPC Classifications
G; G06; G06F; G06F15/00; H; H03; H03K; H03K5/00; H03K5/01; H03K5/04; H03K5/06

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 258 words
A duration-sensitive signal stretcher, for se with a clocked source (20) of control information signals exhibiting one or the other of two alternative signal levels characterized by: delay means (L-1 L-5) having a plurality of successive signal takeoff points; the amount of delay (τ) between successive ones of said takeoff points being the same; the input (Cl) of said delay means being responsive to the output (Cl) of said signal source; a plurality of signal paths, each connected to a respectively different one of said signal takeoff points; an "and" gate (30) having a plurality of inputs equal in number to said plurality of signal paths, each of said signal paths terminating at a respectively different one of said plurality of inputs of said "and" gate; a plurality of delay devices (D-1 to D-8), each imparting the same predetermined amount of delay (τ); and a succession of two-input "or" gates (0-1 to 0-9), with one input of each rendered responsive to the output of said "and" gate; with the output of each of said succession of "or" gates, with the exception of the last (0-9) of said plurality of delay devices to the other input of the next succeeding one of said succession of "or" fates; and with the output of said last of said succession of "or" gates coupled to a control signal output (CO); wherein the sum of the delays imparted by said plurality of delay devices (D-1 to D-8) exceeds the amount of delay between the first and last of said successive signal takeoff points.
Claim 2
Dependent Claim 258 words
A duration-sensitive signal stretcher, for se with a clocked source (20) of control information signals exhibiting one or the other of two alternative signal levels characterized by: delay means (L-1 L-5) having a plurality of successive signal takeoff points; the amount of delay (τ) between successive ones of said takeoff points being the same; the input (Cl) of said delay means being responsive to the output (Cl) of said signal source; a plurality of signal paths, each connected to a respectively different one of said signal takeoff points; an "and" gate (30) having a plurality of inputs equal in number to said plurality of signal paths, each of said signal paths terminating at a respectively different one of said plurality of inputs of said "and" gate; a plurality of delay devices (D-1 to D-8), each imparting the same predetermined amount of delay (τ); and a succession of two-input "or" gates (0-1 to 0-9), with one input of each rendered responsive to the output of said "and" gate; with the output of each of said succession of "or" gates, with the exception of the last (0-9) of said plurality of delay devices to the other input of the next succeeding one of said succession of "or" fates; and with the output of said last of said succession of "or" gates coupled to a control signal output (CO); wherein the sum of the delays imparted by said plurality of delay devices (D-1 to D-8) exceeds the amount of delay between the first and last of said successive signal takeoff points.
Claim 3
Dependent Claim 35 words
Apparatus in accordance with claim 1 wherein said predetermined amount of delay imparted by each of said plurality of delay devices (D-1 to D-8) corresponds to a period at the clocking frequency for said signals.
Claim 4
Dependent Claim 32 words
Apparatus in accordance with claim 1 or 2 wherein the amount of delay between successive ones of said signal takeoff points corresponds to a period at the clocking frequency for said signals.
Claim 5
Dependent Claim 49 words
Apparatus in accordance with claim 1, 2 or 3, also including means, independent of said delay means (L-1 to L-5) and said "and" gate (30), for coupling the output of said signal source (20) to the other input of the first (0-1) of said succession of two-input "or" gates.
Claim 6
Dependent Claim 53 words
Apparatus in accordance with claim 4 wherein delivery of signals from said source (20) to the first of said plurality of successive signal takeoff points is delayed relative to delivery of signals from said source to said other input of the first (0-1) of said succession of two-input "or" gates (0-1 to 0-9).

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