Patent US5396170A successfully refreshed from Google Patents.
EP0199501A2
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CMOS Current sense amplifiers
Assignee: Advanced Micro Devices Inc
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Filing: 1986-04-10
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Granted: —
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Expires: 2006-04-10
Abstract
Abstract A CMOS current sense amplifier circuit for providing a high speed of operation includes a sense amplifier, a dummy sense amplifier and an operational sense amplifier. A memory array is formed of a plurality of core transistors which are arranged in a plurality of rows of word lines and a plurality of columns of bit-lines. A dummy bit-line is formed of a plurality of core transistors which are arranged in parallel along the rows of word lines. A first pass transistor and a plurality of Y-pass transistors are coupled between the sense amplifier and the memory array. Second and third pass transistors are coupled between the dummy sense amplifier and the dummy bit-line. A plurality of N-channel MOS transistors are used to clamp all of the bit-lines ih the array and dummy bit-line to a ground potential. The operational sense amplifier is responsive to the sense amplifier, dummy sense amplifier and the clamping transistors for generating an output signal which has a fast response time when making a low-to-high transition (that is when selecting an unprogrammed memory cell).
Inventors
- 👤 Bhimachar Venkatesh
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 09:56
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/14; G11C7/06; G11C7/062; G11C2207/00; G11C2207/06; G11C2207/063
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
210 words
A CMOS current sense amplifier circuit for providing a high speed of operation comprising: sense amplifier means for providing a first output; a memory array formed of a plurality of core transistors which are arranged in n rows of word lines and m columns of bit-lines; a first pass transistor and a plurality of Y-pass transistors coupled between said sense amplifier means and said first array; dummy sense amplifier means for providing a second ouput; a dummy bit-line formed of a plurality of core transistors which are arranged in parallel along the n rows of word lines; second and third pass transistors coupled between said dummy sense amplifier means and said dummy bit-line; clamping means coupled to said memory array and dummy bit-line for maintaining all of the bit-lines at a ground potential; said first pass transistor, second pass transistor and clamping means being responsive to false and true clamp pulse signals for permitting the quick discharging of the first output of said sense amplifier means and of the second output of said dummy sense amplifier means; and operational sense .amplifier means responsive to said first and second outputs for generating a third output at an output terminal which has a fast response . time when making a low-to-high transition.
Claim 2
Dependent Claim
210 words
A CMOS current sense amplifier circuit for providing a high speed of operation comprising: sense amplifier means for providing a first output; a memory array formed of a plurality of core transistors which are arranged in n rows of word lines and m columns of bit-lines; a first pass transistor and a plurality of Y-pass transistors coupled between said sense amplifier means and said first array; dummy sense amplifier means for providing a second ouput; a dummy bit-line formed of a plurality of core transistors which are arranged in parallel along the n rows of word lines; second and third pass transistors coupled between said dummy sense amplifier means and said dummy bit-line; clamping means coupled to said memory array and dummy bit-line for maintaining all of the bit-lines at a ground potential; said first pass transistor, second pass transistor and clamping means being responsive to false and true clamp pulse signals for permitting the quick discharging of the first output of said sense amplifier means and of the second output of said dummy sense amplifier means; and operational sense .amplifier means responsive to said first and second outputs for generating a third output at an output terminal which has a fast response . time when making a low-to-high transition.
Claim 3
Dependent Claim
36 words
A current sense amplifier circuit as claimed in Claim 1, wherein said sense amplifier means comprises a pair of P-channel MOS transistors, a pair of N-channel MOS transistors, a first output transistor and a load transistor.
Claim 4
Dependent Claim
36 words
A current sense amplifier as claimed in Claim 2, wherein said dummy sense amplifier means comprises a pair of P-channel MOS transistors, a pair of N-channel MOS transistors, a second output transistor, and a load transistor.
Claim 5
Dependent Claim
48 words
A current sense amplifier as claimed in Claim 3, wherein said first pass transistor has its drain connected to said first output transistor, its source connected to the drains of said Y-pass transistors, and its gate connected to a control terminal for receiving the false clamp pulse signal.
Claim 6
Dependent Claim
50 words
A current sense amplifier circuit as claimed in Claim 4, wherein said second pass transistor has its drain connected to said second output transistor, its source connected to the drain of said third pass transistor, and its gate connected to a control terminal for receiving the false clamp pulse signal.
Claim 7
Dependent Claim
66 words
A current sense amplifier circuit as claimed in Claim 5, wherein said clamping means comprises a plurality of N-channel MOS transistors, each transistor having its drain connected to a separate bit-line of the n columns in said memory array and to the dummy bit-line, its source connected to the ground potential and its gate connected to a control terminal for receiving the true clamp pulse signal.
Claim 8
Dependent Claim
36 words
A current sense amplifier as claimed in Claim 6, wherein said operational sense amplifier means comprises a pair of current mirror transistors and a pair of load transistors, a current source, and an output buffer stage.
Claim 9
Dependent Claim
47 words
.A current sense amplifier circuit as claimed in Claim 2, further comprising a first capacitor coupled to the first output of said sense amplifier means which is quicky discharged so as to facilitate the fast low-to-high transition at the third output of said operational sense amplifier means.
Claim 10
Dependent Claim
47 words
A current sense amplifier circuit as claimed in Claim 8, further comprising a second capacitor coupled to said clamping means which is quicky charged up from the ground potential so as to facilitate the fast low-to-high transition at the third output of said operational sense amplifier means.
Claim 11
Dependent Claim
152 words
A high speed CMOS current sense amplifier circuit comprising: means for generating a sense amplifier output; means for generating a dummy sense amplifier output; means responsive to said sense amplifier output and dummy sense amplifier output for generating a differential sense amplifier output; array means formed of a plurality of core transistors which are arranged in a plurality of rows and columns, each column of said core transistors being connected to bit-lines, said array means being operatively connected to said amplifier sense output and said dummy sense amplifier output; clamping means connected to all of the bit-lines of said array means for clamping said bit-lines . to a ground potential so that all bit-lines are required to charge up from the ground level; and output means coupled to said differential sense amplifier output and being responsive to said clamping means for generating an output signal which has a fast low-to-high transition time.
Claim 12
Dependent Claim
152 words
A high speed CMOS current sense amplifier circuit comprising: means for generating a sense amplifier output; means for generating a dummy sense amplifier output; means responsive to said sense amplifier output and dummy sense amplifier output for generating a differential sense amplifier output; array means formed of a plurality of core transistors which are arranged in a plurality of rows and columns, each column of said core transistors being connected to bit-lines, said array means being operatively connected to said amplifier sense output and said dummy sense amplifier output; clamping means connected to all of the bit-lines of said array means for clamping said bit-lines . to a ground potential so that all bit-lines are required to charge up from the ground level; and output means coupled to said differential sense amplifier output and being responsive to said clamping means for generating an output signal which has a fast low-to-high transition time.
Claim 13
Dependent Claim
40 words
A current sense amplifier circuit as claimed in Claim 10, wherein said means for generating the sense amplifier output comprises a pair of P-channel MOS transistors, a pair of N-channel MOS transistors, a load transistor, and a first output transistor.
Claim 14
Dependent Claim
41 words
A current sense amplifier circuit as claimed in Claim 10, wherein said means for generating the dummy sense amplifier output comprises a pair of P-channel MOS transistors, a pair of N-channel MOS transistors, a load transistor, and a second output transistor.
Claim 15
Dependent Claim
32 words
A current sense amplifier circuit as claimed in Claim 10, wherein said differential sense amplifier means comprises a pair of current mirror transistors, a pair of load transistors and a current source.
Claim 16
Dependent Claim
36 words
A current sense amplifier circuit as claimed in Claim 10, further comprising a capacitor coupled to the sense amplifier output which is quickly discharged so as to facilitate the fast low-to-high transition of the output signal.
Claim 17
Dependent Claim
41 words
A current sense amplifier circuit as claimed in Claim 14, further comprising a second capacitor coupled to the clamping means which is quickly charged up from the ground potential so as to facilitate the fast low-to-high transition of the output signal.
Claim 18
Dependent Claim
61 words
A current sense amplifier circuit as claimed in Claim 10, wherein said clamping means comprises a plurality of N-channel MOS transistors, each transistor having its drain connected to one bit-line of the plurality of columns in said array means, its source connected to the ground potential and its gate connected to a control terminal for receiving a true clamp pulse signal.
Claim 19
Dependent Claim
118 words
A high speed CMOS current sense amplifier circuit comprising: differential sense amplifier means for generating an output signal; array means formed of a plurality of core transistors which are arranged in a plurality of rows and columns, each column of said core transistors being connected to bit-lines; - means for connecting said array means to said differential sense amplifier means; clamping means connected to all of the bit-lines in said array means for clamping said bit-lines to a ground potential so that all bit-lines are required to charge up from the ground level; and said differential sense amplifier means being responsive to said clamping means so that the output signal has the fast low to high transition time.
Claim 20
Dependent Claim
118 words
A high speed CMOS current sense amplifier circuit comprising: differential sense amplifier means for generating an output signal; array means formed of a plurality of core transistors which are arranged in a plurality of rows and columns, each column of said core transistors being connected to bit-lines; - means for connecting said array means to said differential sense amplifier means; clamping means connected to all of the bit-lines in said array means for clamping said bit-lines to a ground potential so that all bit-lines are required to charge up from the ground level; and said differential sense amplifier means being responsive to said clamping means so that the output signal has the fast low to high transition time.
Claim 21
Dependent Claim
32 words
A current sense amplifier circuit as claimed in Claim 17, wherein said differential sense amplifier means comprises a pair of current mirror transistors, a pair of load transistors and a current source.
Claim 22
Dependent Claim
27 words
A current sense amplifier circuit as claimed in Claim 17, wherein said connecting means includes first, second and third pass transistors and a plurality of Y-pass transistors.
Claim 23
Dependent Claim
61 words
A current sense amplifier circuit as claimed in Claim 17, wherein said clamping means comprises a plurality of N-channel MOS transistors, each transistor having its drain connected to one bit-line of the plurality of columns in said array means, its source connected to the ground potential, and its gate connected to a control terminal for receiving a true clamp pulse signal.
References Cited (Backward Citations)
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