Arithmetic unit with simple overflow detection system

Claim 1

An arithmetic unit with a simple overflow detection system, said arithmetic unit being arranged to perform arithmetic operations between first and second data, the first data being exclusively divided into a fixed value portion and a variable portion whose digit position is lower than that of the fixed value portion, a ratio of a length of the fixed value portion to that of the variable portion in the first data being adapted to vary, the second data being adapted to correspond only to the variable portion of the first data, characterized by comprising: a mode register (100) for outputting a mode signal which represents the ratio and which is externally supplied in advance; first and second input registers (20, 30) for receiving and storing the first and second data; an adder (40) for adding output data from said first and second input registers (20, 30) in entire lengths thereof; switch means (50, 60) supplied with said mode signal for separating the output data from said first input register (20) and said adder (40) into a fixed value portion and a variable portion, respectively, and outputting the fixed value portion and the variable portion; a comparator (70) for comparing the fixed value portion of the output from said first input register (20) with the fixed value portion of the output from said adder (40), and outputting a coincidence or noncoincidence signal therefor; an output register (80) for linking the fixed value portion of the output from said first input register (20) with the variable portion of the output from said adder (40), and outputting linked data as an arithmetic operation result; and an overflow detector (90) for detecting an overflow of a sum of the variable portions of the first and second data in response to the noncoincidence signal from said comparator (70).