Graded extended drain concept for reduced hot electron effect

Claim 2

A metal oxide semiconductor field effect transistor comprising;

Claim 3

a semiconductor body doped with a first polarity dopant; an insulating layer disposed over a portion of said body; and an electrically conductive gate electrode disposed over said insulating layer so as to be electrically insulated from said semiconductor body; said semiconductor body having a source region heavily doped with a second polarity dopant and a drain region heavily doped with said second polarity dopant, said source and drain regions being disposed in said semiconductor body to a specifed depth on either side of said gate electrode; said semiconductor body also having a lightly doped protrusion extending from at least one of said source and said drain regions, said dopant in said protrusion being a second polarity dopant, each said protrusion being disposed beneath the surface of said semiconductor body and extending toward the region beneath said gate electrode, each said ' protrusion being spaced apart from the boundary between said semiconductor body and said insulating layer and each said protrusion having a graded region substantially surrounding said protrusion, said protrusion also including at least two second polarity dopants exhibiting distinct diffusivity characteristics.

Claim 4

a semiconductor body doped with a first polarity dopant; an insulating layer disposed over a portion of said body; and an electrically conductive gate electrode disposed over said insulating layer so as to be electrically insulated from said semiconductor body; said semiconductor body having a source region heavily doped with a second polarity dopant and a drain region heavily doped with said second polarity dopant, said source and drain regions being disposed in said semiconductor body to a specifed depth on either side of said gate electrode; said semiconductor body also having a lightly doped protrusion extending from at least one of said source and said drain regions, said dopant in said protrusion being a second polarity dopant, each said protrusion being disposed beneath the surface of said semiconductor body and extending toward the region beneath said gate electrode, each said ' protrusion being spaced apart from the boundary between said semiconductor body and said insulating layer and each said protrusion having a graded region substantially surrounding said protrusion, said protrusion also including at least two second polarity dopants exhibiting distinct diffusivity characteristics.

Claim 5

The transistor of claim 1 further including side spacers on either side of said gate electrode.

Claim 6

The transistor of claim 2 in which said spacers are between approximately 0.1 and 0.2 microns in width.

Claim 7

The device of claim 1 in which said protrusions extend outwardly from adjacent heavily doped portions for a distance of between approximately 0.1 and 0.2 microns.

Claim 8

The transistor of claim 1 in which said protrusions are disposed approximately 1,000 angstroms below the interface between said oxide and said semiconductor body.

Claim 9

The transistor of claim 1 in which said heavily doped regions extend approximately from the surface of said semiconductor body to a depth of between approximately 1,500 and 4,000 angstroms therein.

Claim 10

The transistor of claim 1 in which said first polarity dopant comprises a p-type dopant and said second type dopant comprises an n-type dopant.

Claim 11

The transistor of claim 1 in which said transistor is an n-channel device.

Claim 12

The transistor of claim 1 in which said one of said light dopants comprises arsenic.

Claim 13

The transistor of claim 1 in which said one of said light dopants comprises phosphorous.

Claim 14

The transistor of claim 1 in which said semiconductor body comprises silicon.

Claim 15

The transistor of claim 1 in which said said semiconductor body comprises an n-doped semiconductor substrate including a p-doped well therein.

Claim 16

The transistor of claim 1 in which said insulating layer comprises silicon oxide.

Claim 17

The transistor of claim 1 in which said electrically conductive gate comprises material selected from the group consisting of metals and doped polycrystalline silicon.

Claim 18

The transistor of claim 1 in which said heavily doped region is formed at an implant dosage of approximately 8 x 10" atoms of dopant per square centimeter.

Claim 19

The transistor of claim 1 in which said lightly doped regions are formed at an implant dosage of between approximately 10 12 and 10" dopant atoms per square centimeter.

Claim 22

The method of claim 17 in which said high diffusivity dopant is implanted first.

Claim 23

The method of claim 17 in which said high diffusivity dopant comprises phosphorous.

Claim 24

The method of claim 17 in which said lower diffusivity dopant comprises arsenic.