EP0198231A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Data processor with parallel instruction control and execution
Assignee: Hitachi Microcomputer System Ltd
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Filing: 1986-03-14
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Granted: —
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Expires: 2006-03-14
Abstract
Abstract A data processor (1) for executing instructions using operand data stored in a main memory (5) comprises an instruction control unit (3) having a first associative memory (31) storing instructions read out from the main memory, and an instruction controller (300) reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory, and outputting the instruction to be executed; and an instruction execution unit (4) having a second associative memory (21) storing operand data read out from the main memory, and an instruction executioner (400) executing the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
Inventors
- 👤 Tadahiko Nishimukai
- 👤 Atsushi Hasegawa
- 👤 Kunio Uchiyama
- 👤 Ikuya Kawasaki
- 👤 Makoto Hanawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-10 02:33
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/28; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30047; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0846; G06F12/0848; G06F12/0891; G06F9/30043; G06F9/38; G06F9/3802; G06F9/3824
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
396 words
A data processor for use with a main memory in which operand data and instructions are stored comprising: (a) an instruction control unit (3) including: i) a first associative memory (31) for storing instructions having an address input and an instruction output, and ii) an instruction controller (300) having a first, instruction address, output coupled to said address input of said fist associative memory and an instruction input coupled to said instruction output of said first associative memory and second and third outputs for outputting an instruction and an instruction address respectively; (b) an instruction execution unit (4) including: (i) a second associative memory (21) for storing operand data having an address input and an operand data output, and (ii) an instruction executioner (400) having an operand data address output coupled to address input of said second associative memory, a first, operand data, input coupled to said operand data output of said second associative memory, and second and third inputs coupled to said second and third outputs of said instruction control unit, respectively; (c) an interface unit (2) having as first and second inputs, said first output of said instruction controller and said operand data address output from said instruction executioner and having first and second outputs coupled to said instruction input of said instruction controller and said operand data input of said instruction executioner, respectively and a third output and a third input each for coupling to a main memory, said interface unit including a selector (22) for selectively coupling one of said first and second inputs to said third output and said third input to one of said first and second outputs; and (d) means for disabling operation of said interface unit when either said first instruction address or said operand data address received thereby is present in said first or said second associative manory , respectively, whereby said instruction controller will read out an instruction from said first associative memory when the instruction is present in said first associative memory and from the main memory when the instruction is not present in said first associative memory, and said instruction executioner will execute its instruction by using operand data read out from said second associative memory when the operand data is present in said second associative memory and from the main memory when said operand data is not present in said second associative memory.
Claim 2
Dependent Claim
396 words
A data processor for use with a main memory in which operand data and instructions are stored comprising: (a) an instruction control unit (3) including: i) a first associative memory (31) for storing instructions having an address input and an instruction output, and ii) an instruction controller (300) having a first, instruction address, output coupled to said address input of said fist associative memory and an instruction input coupled to said instruction output of said first associative memory and second and third outputs for outputting an instruction and an instruction address respectively; (b) an instruction execution unit (4) including: (i) a second associative memory (21) for storing operand data having an address input and an operand data output, and (ii) an instruction executioner (400) having an operand data address output coupled to address input of said second associative memory, a first, operand data, input coupled to said operand data output of said second associative memory, and second and third inputs coupled to said second and third outputs of said instruction control unit, respectively; (c) an interface unit (2) having as first and second inputs, said first output of said instruction controller and said operand data address output from said instruction executioner and having first and second outputs coupled to said instruction input of said instruction controller and said operand data input of said instruction executioner, respectively and a third output and a third input each for coupling to a main memory, said interface unit including a selector (22) for selectively coupling one of said first and second inputs to said third output and said third input to one of said first and second outputs; and (d) means for disabling operation of said interface unit when either said first instruction address or said operand data address received thereby is present in said first or said second associative manory , respectively, whereby said instruction controller will read out an instruction from said first associative memory when the instruction is present in said first associative memory and from the main memory when the instruction is not present in said first associative memory, and said instruction executioner will execute its instruction by using operand data read out from said second associative memory when the operand data is present in said second associative memory and from the main memory when said operand data is not present in said second associative memory.
Claim 3
Dependent Claim
136 words
A data processor according to claim 1, wherein said first associative memory (31) provides an end of fetch signal at the end of a fetch, and said instruction controller (300) further includes: a first-in first-out memory (34) having an input for information to be stored coupled to said instruction output of said first associative memory and an output at which said second, instruction, output of said instruction controller is provided, said first-in first-out memory providing a control output when it is vacant; a control circuit having as inputs said end of fetch signal and said control signal and providing as an output a renewal signal; and an address generator (32) having as an input said renewal signal and providing as outputs said first instruction address, output, and said third, instruction address, output of said instruction controller.
Claim 4
Dependent Claim
68 words
A data processor according to claim 1, wherein said instruction executioner (400) includes a ROM (41) having as an input said third, instruction address, output of said instruction controller and outputting control information, and a processor (45), having as inputs said control information, said second instruction, output of said instruction controller and said operand data for executing said instruction by using said control information and said operand data.
Claim 5
Dependent Claim
47 words
A data processor according to claim 1, wherein said first associative memory (31) has a first location field for storing an instruction address, a first data field storing an instruction and a first effective bit indicating whether or not said instruction in said data field is effective.
Claim 6
Dependent Claim
39 words
A data processor according to claim 1, wherein said second associative memory (21) has an operand buffer for storing operand data and a line buffer for storing byte data of which the length is determined by the operand size.
Claim 7
Dependent Claim
49 words
A data processor according to claim 5, wherein said operand buffer has a second location field for storing a operand data address, a second data field for storing operand data and a second effective bit for indicating whether or not operand data in said second data field is effective.
Claim 8
Dependent Claim
45 words
A data processor according to claim 5, wherein said line buffer has a third location field for storing a byte data address, third data fields for storing byte data and third effective bits for indicating whether or not said associated third data fields are effective.
Claim 9
Dependent Claim
160 words
A data processor for executing an instruction using operand data stored in a main memory comprising: an instruction control unit (3) having a first associative memory (31) for storing instructions read out from a main memory, and an instruction controller (300) adapted to read out an instruction from said first associative memory when said instruction is present in said first associative memory (31) and from a main memory (5) when said instruction is not present in said first associative memory (31), and providing as an ouput the instruction to be executed, and an instruction execution unit (4) having a second associative memory (21) for storing operand data read out from a main memory, and an instruction executioner (400) for executing said instruction using operand data read out from said second associative memory when said operand data is present in said second associative memory and from a main memory when said operand data is not present in said second associative memory.
Claim 10
Dependent Claim
160 words
A data processor for executing an instruction using operand data stored in a main memory comprising: an instruction control unit (3) having a first associative memory (31) for storing instructions read out from a main memory, and an instruction controller (300) adapted to read out an instruction from said first associative memory when said instruction is present in said first associative memory (31) and from a main memory (5) when said instruction is not present in said first associative memory (31), and providing as an ouput the instruction to be executed, and an instruction execution unit (4) having a second associative memory (21) for storing operand data read out from a main memory, and an instruction executioner (400) for executing said instruction using operand data read out from said second associative memory when said operand data is present in said second associative memory and from a main memory when said operand data is not present in said second associative memory.
Claim 11
Dependent Claim
28 words
A data processor according to claim 1 or claim 8, wherein said instruction control unit (3) and said instruction execution unit (4) are formed on a single chip.
Claim 12
Dependent Claim
54 words
A data processor according to any of the claims 1 to 9, further comprising a purge controller (6) having as an output a purge instruction signal making said first and second associative memories ineffective before executing said instruction when the address on said single chip corresponds to an address assigned to an external unit.
Claim 13
Independent Claim
120 words
A method of data processing comprising the steps of: reading out an instruction from a first associative memory (31) when said instruction is present in said first associative memory and from a main memory (5) when said instruction is not present in said first associative memory; storing said instruction read out from said first associative memory (31) or said main memory (5); analyzing said instruction and storing the analyzed result; reading out operand data from a second associative memory (21) when said operand data is present in said second associative memory and from a main memory when said operand data is not present in said second associative memory, executing said instruction by using said analyzed result and said operand data.
Claim 14
Independent Claim
120 words
A method of data processing comprising the steps of: reading out an instruction from a first associative memory (31) when said instruction is present in said first associative memory and from a main memory (5) when said instruction is not present in said first associative memory; storing said instruction read out from said first associative memory (31) or said main memory (5); analyzing said instruction and storing the analyzed result; reading out operand data from a second associative memory (21) when said operand data is present in said second associative memory and from a main memory when said operand data is not present in said second associative memory, executing said instruction by using said analyzed result and said operand data.
Claim 15
Dependent Claim
33 words
A method of data processing according to claim 11, further comprising the step of: storing said instruction in said first associative memory when said instruction is not present in said first associative memory.
Claim 16
Dependent Claim
38 words
A method of data processing according to claim 11 or claim 12, further comprising the step of: storing said operand data in said second associative memory when said operand data is not present in said second associative memory.
Claim 17
Independent Claim
30 words
A method of data processing according to any of the claims 11 to 13, further comprising the step of: purging said first and second associative memories before executing said instruction.
References Cited (Backward Citations)
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