A method and an apparatus for modeling bit rate justification

Claim 1

A method for modeling bit rate justification comprising following steps: - transforming and shifting the spectrum of basic jitter in a positive/zero/negative bit rate justification from zero frequency range to higher frequency range; - passing the high frequency converted version of the basic jitter through a phase locked loop; and - leaving only an amount of jitter in the output which is negligible.

Claim 2

A method for modeling bit rate justification comprising following steps: - transforming and shifting the spectrum of basic jitter in a positive/zero/negative bit rate justification from zero frequency range to higher frequency range; - passing the high frequency converted version of the basic jitter through a phase locked loop; and - leaving only an amount of jitter in the output which is negligible.

Claim 4

An apparatus for bit rate justification comprising a bit rate justification part which includes in a serial connection: - a first justificator (1) , a correlator (2), a buffer (3) and a second justificator (4), whereby . the first justification circuit receives a frame structure signal (A), the buffer (3) receives a tributary clock signal (B) and the output of the correlator (2) and the second justification circuit (4) carries out a second justification process on the basis of the output of the correlator under the control of the auxiliary signals of the output of the correlator (2) and the output of the second justification circuit (4) is passed through a justification transfer circuit (6) to a read-out control port of a store /retrieve buffer (8) receiving as further inputs the tributary clock signal (B) and a tributary code ( C ), the code (C) being read out from the read-out port of the store/retrieve buffer (8) in accordance with the frame structure and the results of the justification and supplied to an adder (7) which adds it to the output of a stuffing signal constructor (5) which receives as its input signals the output of the first justification circuit (1) . and the output of the second justification curcuit (4); and a bit rate recovery part including: an instruction detector (12), a correlation detector (9), an information-carrying time slot recovery circuit (10), a pre-smoother (11), a store/retrieve buffer (13) and a phase locked loop (14), whereby the instruction detector (12) detects stuffing instructions from the receive code (D), the correlation detector (9) verifies and detects the stuffing instructions from the receive code (D) on the basis of the character of the fixed bit rate in the first justification process, the outputs of the detectors (9 and 12) are fed to the information carrying time slot recovery circuit (10) from which the tributary information-carrying time slot signal is obtained to write the tributary code (D) in the store/retrieve buffer (13) from which a tributary code (F) is read out with the tributary read out clock signal which is provided by the phase locked loop (14), and the pre-smoother (11) receives an input clock signal (E) the rate of which equals to the rate of the information-carrying time slot signal and the output pulse of the pre-smoothing circuit (11) is fed to the phase locked loop (14) with the bit rate which equals to the tributary frequency.

Claim 5

An apparatus for bit rate justification comprising a bit rate justification part which includes in a serial connection: - a first justificator (1) , a correlator (2), a buffer (3) and a second justificator (4), whereby . the first justification circuit receives a frame structure signal (A), the buffer (3) receives a tributary clock signal (B) and the output of the correlator (2) and the second justification circuit (4) carries out a second justification process on the basis of the output of the correlator under the control of the auxiliary signals of the output of the correlator (2) and the output of the second justification circuit (4) is passed through a justification transfer circuit (6) to a read-out control port of a store /retrieve buffer (8) receiving as further inputs the tributary clock signal (B) and a tributary code ( C ), the code (C) being read out from the read-out port of the store/retrieve buffer (8) in accordance with the frame structure and the results of the justification and supplied to an adder (7) which adds it to the output of a stuffing signal constructor (5) which receives as its input signals the output of the first justification circuit (1) . and the output of the second justification curcuit (4); and a bit rate recovery part including: an instruction detector (12), a correlation detector (9), an information-carrying time slot recovery circuit (10), a pre-smoother (11), a store/retrieve buffer (13) and a phase locked loop (14), whereby the instruction detector (12) detects stuffing instructions from the receive code (D), the correlation detector (9) verifies and detects the stuffing instructions from the receive code (D) on the basis of the character of the fixed bit rate in the first justification process, the outputs of the detectors (9 and 12) are fed to the information carrying time slot recovery circuit (10) from which the tributary information-carrying time slot signal is obtained to write the tributary code (D) in the store/retrieve buffer (13) from which a tributary code (F) is read out with the tributary read out clock signal which is provided by the phase locked loop (14), and the pre-smoother (11) receives an input clock signal (E) the rate of which equals to the rate of the information-carrying time slot signal and the output pulse of the pre-smoothing circuit (11) is fed to the phase locked loop (14) with the bit rate which equals to the tributary frequency.