An electronic postage meter having power up and power down protection circuitry

Abstract

Abstract 57 A method and apparatus (80) for providing enhanced security to the non-volatile memory (50, 60) of an electronic postage meter during power up and power down of the meter is disclosed. The apparatus (80) comprises means for detecting a regulated voltage level of the meter, means for detecting an unregulated voltage level of the meter, means for detecting a predetermined frequency from a system clock associated with the meter and a reset delay circuit responsive to the detected unregulated voltage, detected regulated voltage and the predetermined clock frequency for allowing access to the non-volatile memories (50, 60) if the unregulated voltage level, the regulated level and the clock frequency have reached their appropriate levels and preventing access to the memories (50, 60) other- ' wise. Through the use of this circuitry the critical accounting information within the memories (50, 60) is protected during the powering up and powering down of the postage meter.

Inventors

• 👤 Peter C. Digiulio
• 👤 Warren G. Hafner
• 👤 Henry Stalzer

Bibliographic Details