EP0196915A2
Expired / Lapsed
EP
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Thin film transistor array and method of manufacturing same
Assignee: Panasonic Holdings Corp
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Filing: 1986-04-01
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Granted: —
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Expires: 2006-04-01
Abstract
Abstract A self-aligned TFT array for liquid crystal display devices and a method of manufacturing the array are disclosed. A protective insulating layer (6) on a semiconductor layer (5) is exactly aligned with a gate electrode (2). A self-alignment method is used for patterning the protective insulating layer and an impurity-doped semiconductor layer on the semiconductor layer. No lift-off process is necessary.
Inventors
- 👤 Mamoru Takeda
- 👤 Ichiro Yamashita
- 👤 Isamu Kitahiro
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 20:51
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/1368; H10D30/673; H10D30/6732; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6746; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/949
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
120 words
A thin film transistor array comprising: a transparent insulating substrate (1); a gate electrode (2) formed on said substrate (1); a gate insulating layer (4) formed on said substrate and said gate electrode (2); A semiconductor layer (5) formed on said gate insulating layer; a protective insulating layer (6) formed on said semiconductor layer at a portion above said gate electrode (2) to be aligned with said gate electrode; an impurity-doped semiconductor layer (7) formed on said semiconductor layer (5) at a portion beside said portion on which said protective insulating layer (6) is formed; and source and drain electrodes (9a, 9b) formed on said impurity-doped semiconductor layer (7) and partly on a part of said protective insulating layer (6).
Claim 2
Dependent Claim
120 words
A thin film transistor array comprising: a transparent insulating substrate (1); a gate electrode (2) formed on said substrate (1); a gate insulating layer (4) formed on said substrate and said gate electrode (2); A semiconductor layer (5) formed on said gate insulating layer; a protective insulating layer (6) formed on said semiconductor layer at a portion above said gate electrode (2) to be aligned with said gate electrode; an impurity-doped semiconductor layer (7) formed on said semiconductor layer (5) at a portion beside said portion on which said protective insulating layer (6) is formed; and source and drain electrodes (9a, 9b) formed on said impurity-doped semiconductor layer (7) and partly on a part of said protective insulating layer (6).
Claim 3
Dependent Claim
123 words
A thin film transistor array comprising: a transparent insulating substrate (1); a gate electrode (2) formed on said substrate; a gate insulating layer (4) formed on said substrate (1) and said gate electrode (2); a semiconductor layer (5) formed on said gate insulating layer (4); a protective insulating layer (6) formed on said semiconductor layer at a portion above said gate electrode (2) to be aligned with said gate electrode; an impurity-doped semiconductor layer (7) formed on said semiconductor layer (5) and said protective insulating layer (6); a third metal layer (11) formed.on said impurity-doped semiconductor layer (7); and source and drain electrodes (9a, 9b) formed on said third metal layer (8) and partly on a part of said protective insulating layer (6).
Claim 4
Dependent Claim
123 words
A thin film transistor array comprising: a transparent insulating substrate (1); a gate electrode (2) formed on said substrate; a gate insulating layer (4) formed on said substrate (1) and said gate electrode (2); a semiconductor layer (5) formed on said gate insulating layer (4); a protective insulating layer (6) formed on said semiconductor layer at a portion above said gate electrode (2) to be aligned with said gate electrode; an impurity-doped semiconductor layer (7) formed on said semiconductor layer (5) and said protective insulating layer (6); a third metal layer (11) formed.on said impurity-doped semiconductor layer (7); and source and drain electrodes (9a, 9b) formed on said third metal layer (8) and partly on a part of said protective insulating layer (6).
Claim 5
Dependent Claim
32 words
A thin film transistor array according to claim 1 or 2, further comprising a transparent pixel electrode (10) formed on said gate insulating layer (4) for driving a liquid crystal display pixel.
Claim 6
Dependent Claim
33 words
A thin film transistor array according to claim 1, 2 or 3, further comprising a transparent pixel electrode (10) formed on said transparent insulating substrate (1) for driving a liquid crystal display pixel.
Claim 7
Dependent Claim
43 words
A thin film transistor array according to any one of claims 1 to 4, further comprising a transparent pixel electrode (10) formed partly on said gate insulating layer (4) and partly on said drain electrode (9b) for driving a liquid crystal display pixel.
Claim 8
Dependent Claim
50 words
A thin film transistor array according to any one of claims 1 to 4, wherein each of said source and drain electrodes (9a, 9b) has a barrier metal layer (8) for preventing a material of each of said source and drain electrodes (9a, 9b) from diffusing into said semiconductor layers.
Claim 9
Independent Claim
240 words
A method of manufacturing a thin film transistor array comprising the steps of: forming a semiconductor layer (5) and a protective insulating layer (6) in turn on a gate insulating layer (4) formed on a transparent insulating substrate (1) and a gate electrode (2) on said transparent insulating substrate; forming a positive resist film (13) on said protective insulating layer; patterning said positive resist film (13) by a self-alignment method using said gate electrode (2) as a phctomask into a pattern aligned with said gate electrode; patterning said protective insulating layer by using said pattern resist film as a mask into a pattern aligned with said gate electrode (2); forming a impurity-doped semiconductor layer (7) on said semiconductor layer and said patterned protective insulating layer; forming a negative resist film (14) on said impurity-doped semiconductor layer, patterning said negative resist film by a self-alignment method using said gate electrode (2) as a photomask into a pattern in which a removed portion of said negative resist film is aligned with said gate electrode; patterning said impurity-doped semiconductor layer by using said patterned negative resist film as a mask so that said impurity-doped semiconductor layer is removed at a portion on said patterned protective insulating layer; patterning said impurity-doped semiconductor layer and said semiconductor layer into a specific pattern; and forming source and drain electrodes (9a, 9b) on said impurity-doped semiconductor layer and partly on a part of said protective insulating layer.
Claim 10
Independent Claim
240 words
A method of manufacturing a thin film transistor array comprising the steps of: forming a semiconductor layer (5) and a protective insulating layer (6) in turn on a gate insulating layer (4) formed on a transparent insulating substrate (1) and a gate electrode (2) on said transparent insulating substrate; forming a positive resist film (13) on said protective insulating layer; patterning said positive resist film (13) by a self-alignment method using said gate electrode (2) as a phctomask into a pattern aligned with said gate electrode; patterning said protective insulating layer by using said pattern resist film as a mask into a pattern aligned with said gate electrode (2); forming a impurity-doped semiconductor layer (7) on said semiconductor layer and said patterned protective insulating layer; forming a negative resist film (14) on said impurity-doped semiconductor layer, patterning said negative resist film by a self-alignment method using said gate electrode (2) as a photomask into a pattern in which a removed portion of said negative resist film is aligned with said gate electrode; patterning said impurity-doped semiconductor layer by using said patterned negative resist film as a mask so that said impurity-doped semiconductor layer is removed at a portion on said patterned protective insulating layer; patterning said impurity-doped semiconductor layer and said semiconductor layer into a specific pattern; and forming source and drain electrodes (9a, 9b) on said impurity-doped semiconductor layer and partly on a part of said protective insulating layer.
Claim 11
Independent Claim
207 words
A method of manufacturing a thin film transistor array comprising the steps of: forming a semiconductor layer (5) and a protective insulating layer (6) in turn on a gate insulating layer (4) formed on a transparent insulating substrate (1) and a gate electrode (2) on said transparent insulating substrate; forming a positive resist film (13) on said protective insulating layer (6); patterning said positive resist film (13) by a self-alignment method using said gate electrode as a photomask into a pattern aligned with said gate electrode; patterning said protective insulating layer by using said patterned resist film as a mask into a pattern aligned with said gate electrode (2); forming an impurity-doped semiconductor layer (7) on said semiconductor layer and said patterned protective insulating layer; forming a third metal layer (11) on said impurity-doped semiconductor layer; patterning said third metal layer (11) into a specific pattern covering a portion including a channel portion above said gate electrode (2); patterning said impurity-doped semiconductor layer and said semiconductor layer by using said patterned third metal layer as a mask; forming source and drain electrodes (9a, 9b) on said gate insulating layer and a part of said third metal layer (11) not including a portion above said protective insulating layer.
Claim 12
Independent Claim
207 words
A method of manufacturing a thin film transistor array comprising the steps of: forming a semiconductor layer (5) and a protective insulating layer (6) in turn on a gate insulating layer (4) formed on a transparent insulating substrate (1) and a gate electrode (2) on said transparent insulating substrate; forming a positive resist film (13) on said protective insulating layer (6); patterning said positive resist film (13) by a self-alignment method using said gate electrode as a photomask into a pattern aligned with said gate electrode; patterning said protective insulating layer by using said patterned resist film as a mask into a pattern aligned with said gate electrode (2); forming an impurity-doped semiconductor layer (7) on said semiconductor layer and said patterned protective insulating layer; forming a third metal layer (11) on said impurity-doped semiconductor layer; patterning said third metal layer (11) into a specific pattern covering a portion including a channel portion above said gate electrode (2); patterning said impurity-doped semiconductor layer and said semiconductor layer by using said patterned third metal layer as a mask; forming source and drain electrodes (9a, 9b) on said gate insulating layer and a part of said third metal layer (11) not including a portion above said protective insulating layer.
Claim 13
Dependent Claim
33 words
A method according to claim 7 or 8, further comprising a step of forming a transparent pixel electrode on said gate insulating layer before the step of forming said source and drain electrodes.
Claim 14
Dependent Claim
29 words
A method according to claim 7 or 8, further comprising a step of forming a transparent pixel electrode on said transparent insulating substrate before forming said gate insulating layer.
Claim 15
Dependent Claim
37 words
A method according to claim 7 or 8, further comprising a step of forming a transparent pixel electrode on said gate insulating layer and said drain electrode after ths step of forming said source and drain electrodes.
References Cited (Backward Citations)
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