Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
166 words
An automatic gain control detection circuit comprising a current source (13), a reference voltage source (E2), input terminal means (11A, 11B), an output terminal means (12A, 12B), a power supply source (E3); CHARACTERIZED IN THAT said detection circuit further comprises first to fourth transistors Q21 to Q24) whose emitters are connected in common to said current source (13), first collector load means (R21) connected between said power supply source (E3) and a node connecting the collectors of said first and second transistors (Q21, Q22) in common, second collector load means (R22) connected between said power supply source (E3) and another node connecting the collectors of said third and fourth transistors (Q23, Q24) in common, and wherein the bases of said first and second transistors (Q21, Q22) are connected in common to said reference voltage source (E2), the bases of sid third and fourth transistors (Q23, Q24) are connected to said input terminals (11A, 11B), and said output terminals (12A, 12B) are respectively connected to said nodes.
Claim 2
Dependent Claim
166 words
An automatic gain control detection circuit comprising a current source (13), a reference voltage source (E2), input terminal means (11A, 11B), an output terminal means (12A, 12B), a power supply source (E3); CHARACTERIZED IN THAT said detection circuit further comprises first to fourth transistors Q21 to Q24) whose emitters are connected in common to said current source (13), first collector load means (R21) connected between said power supply source (E3) and a node connecting the collectors of said first and second transistors (Q21, Q22) in common, second collector load means (R22) connected between said power supply source (E3) and another node connecting the collectors of said third and fourth transistors (Q23, Q24) in common, and wherein the bases of said first and second transistors (Q21, Q22) are connected in common to said reference voltage source (E2), the bases of sid third and fourth transistors (Q23, Q24) are connected to said input terminals (11A, 11B), and said output terminals (12A, 12B) are respectively connected to said nodes.
Claim 3
Dependent Claim
37 words
An automatic gain control detection circuit detection circuit according to claim 1, wherein said third and fourth transistors (Q23, Q24) are set their base potentials equal to a reference voltage provided by said reference voltage source (E2).
Claim 4
Dependent Claim
42 words
An automatic gain control detection circuit detection circuit according to claim 1, wherein said third and fourth transistors (Q23, Q24) are set their base potentials to have a predetermined potential difference from a reference voltage provided by said reference voltage source (E2).
Claim 5
Dependent Claim
45 words
4 . An automatic gain control detection circuit detection circuit according to claim 1, wherein said automatic gain control detection circuit further comprises an input signal processing circuit (11) which provides said input terminals (11A, 11B) with an input signal proportional to the absolute temperature.
Claim 6
Dependent Claim
25 words
An automatic gain control detection circuit as claimed in claim 1, in which said current source (13) provides a current proportional to the absolute temperature.