EP0196586B1
Expired / Lapsed
EP
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Static semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1986-03-24
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Granted: 1993-01-20
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Expires: 2006-03-24
Abstract
No abstract record available.
Inventors
- 👤 Takayuki Ohtani
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 15:09
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/18; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
178 words
A semiconductor memory device comprising: a memory cell array including memory cells (41) arrayed in a matrix, said array divided into a plurality of sections; paired bit lines (BL, BL ) for writing and reading out data to and from selected memory cells (41), a pair of said bit lines being provided for each column and connected to memory cells (41) in the corresponding column; word lines (WL) connected to corresponding memory cells (41) to select memory cells (41) in the row direction; and precharging means (81 to 93) connected to said bit lines (BL, BL ), said precharge means responsive to an address signal to charge said bit lines (BL, BL ) in at least one selected section (11) during only a predetermined period after the address signal varies, characterized in that: said word lines are arranged to be inactive in a deselected section; and said precharge means (81 to 93) is arranged to perform a fast precharge in any selected section during said predetermined period and to perform a relatively slow precharge in said non-selected section.
Claim 2
Dependent Claim
67 words
A semiconductor memory device according to claim 1, characterized in that said semiconductor memory device further includes means (13) for driving said word lines, said word line drive means activates the voltages of said word lines (WL) corresponding to the address signal after the charging of said bit lines (BL, BL ) in said selected section (11) by said precharge means (81 to 93) is substantially completed.
Claim 3
Dependent Claim
118 words
A semiconductor memory device according to claim 1, characterized in that said precharge means includes: first precharge transistor means (81,87) and second precharge transistor means (83,89) connected to said bit lines (BL, BL ) and to a predetermined voltage; means (111,117) for detecting a change in a received address signal; and means (21) for turning on during said predetermined period said second precharge transistor means (83, 89) connected to said bit lines (BL, BL ) in said selected section (11) according to the output signal of said address signal change detecting means (111, 117), and for turning on said first precharge transistor means (81, 87) connected to said bit lines (BL, BL ) of said nonselected section (11).
Claim 4
Dependent Claim
139 words
A semiconductor memory device according to claim 3, characterized in that said precharge MOS transistor means includes at least one first transistor (83, 89) and at least one second transistor (81, 87) connected to said bit lines (BL, BL ) and to said predetermined voltage, said turning on means, according to the output signal of said address signal change detecting means (111, 117), turns on said first transistors (83, 89) in the selected section during said predetermined period, turns off said second transistors (81, 87) connected to said bit lines (BL, BL ) in said selected section (11), turns off said first transistors (83, 89) connected to said bit lines (BL, BL ) in the nonselected section (11), and turns on said second transistors (81, 87) connected to said bit lines (BL, BL ) of the nonselected section (11).
Claim 5
Dependent Claim
31 words
A semiconductor memory device according to claim 4, characterized in that the current feed ability of said first transistor (83, 69) is larger than that of said second transistor (81, 87).
Claim 6
Dependent Claim
59 words
A semiconductor memory device according to claim 3, characterized by further comprising N channel MOS transistors (131, 133), of which the current path is connected at one end to said bit lines (BL, BL ) and at the other end to said predetermined voltage, and of which the gate is connected to the other end of said current path.
Claim 7
Dependent Claim
90 words
A semiconductor memory device according to claim 4, characterized by further comprising third MOS transistors (93) provided for each column, the current path of each of said third transistors (93) being connected at one end to one of said paired bit lines (BL) in said column, and at the other end to the other bit line ( BL ), said turning on means turns on said third transistor (93) when said first transistor (83, 89) is turned on, and equalizes the voltages of both said bit lines (BL, BL ).
Claim 8
Dependent Claim
170 words
A semiconductor memory device according to claim 4, characterized by further comprising column select means (61) connected to said bit lines (BL, BL ) for coupling said bit lines (BL, B L) in said selected section in the read out mode to sense lines (SL, SL ) connected to the output terminal of said column select means, a pair of said sense lines being provided for each column; sense amplifiers (17) connected to said sense lines (SL, SL ) for sensing the voltages in said sense lines (SL, SL ) and amplifying the sensed voltage; transistor means (161, 163) for pulling up voltage of sense lines, connected to said sense lines and said predetermined voltage; and characterized in that said turning on means (21) turns off said sense line pulling up transistor means (161, 163) in said selected section and turns on said sense line pulling up transistor means (161, 163) in said nonselected section to pull up the voltage of said sense lines (161, 163) in said nonselected section.
References Cited (Backward Citations)
No citation records indexed.
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