EP0196475A1
Expired / Lapsed
EP
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Noncontact testing of integrated circuits
Assignee: International Business Machines Corp
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Filing: 1986-03-04
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Granted: —
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Expires: 2006-03-04
Abstract
Abstract tV The method comprising covering metal test pads ( 4 ) of an integrated circuit chip-to-test (11), with a photon-transmissive passivation layer (2) susceptible to photon assisted tunneling, covering the layer (2) with a thin conductive photon- transparent overlayer (3), and then accessing the test pads through the passivation layer and conductive overlayer, by a pulsed laser to provide voltage-modulated photon-assisted tunneling through the insulation layer, to the conductive overlayer as an electron current, and detecting the resulting electron current, thus providing a nondestructive test of integrated circuits. The passivation, normally present to protect the integrated circuit, also lowers the threshold for photoelectron emission. The conductive overlayer acts as a photoelectron collector for the detector. A chip-to-test which is properly designed for photon assisted tunneling testing has test sites accessible to laser photons even though passivated. Such a chip-to-test may be nondestructively tested in air at one or several stages of its processing, without the sacrifices of mechanical probing or of bringing test sites out to output pads.
Inventors
- 👤 Johannes Georg Beha
- 👤 Russell Earren Dreyfus
- 👤 Allan Mark Hartstein
- 👤 Gary Wayne Rubloff
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 22:16
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/302; G01R31/308; H; H10; H10P; H10P74/00; H10P74/20; H10P74/207
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
246 words
A method of testing an integrated circuit chip-to-test, characterised in that each integrated circuit to be placed under test has at least one conductive test site (4), the test sites are covered by a passivation layer (2), the passivation layer being of a material which is photon transmissive and susceptible to photon assisted tunneling, a thin conductive overlayer (3) is provided over the passivation layer (2), the overlayer being penetrable by photons, integrated circuit test exercise means are applied to the chip-to-test to cause electronic activity in the chip-to-test appropriate to the desired test, as as to provide at a given test site a voltage potential related to operation, pulse laser means (6) are operated to access a selected test site on the chip-to-test as as to excite photoemission at values related to the instantaneous voltage potential at the accessed test site whereby the accessed test site provides via photon assisted tunneling through the passivating layer (2) to the conductive overtayer (3) differing values of electron currents as a function of operation voltage differences, and current measurement means (9) is connected to the overlayer (3) to take readings of tunneling electron currents which in turn are a composite function of the laser light excitation of the test sites and the instantaneous voltage at such test sites; whereby the test site accessed by the pulsed taser provides differing readings for proper operation and for faulty operations; and the integrating circuit may be tested without destructive contact probing.
Claim 2
Independent Claim
246 words
A method of testing an integrated circuit chip-to-test, characterised in that each integrated circuit to be placed under test has at least one conductive test site (4), the test sites are covered by a passivation layer (2), the passivation layer being of a material which is photon transmissive and susceptible to photon assisted tunneling, a thin conductive overlayer (3) is provided over the passivation layer (2), the overlayer being penetrable by photons, integrated circuit test exercise means are applied to the chip-to-test to cause electronic activity in the chip-to-test appropriate to the desired test, as as to provide at a given test site a voltage potential related to operation, pulse laser means (6) are operated to access a selected test site on the chip-to-test as as to excite photoemission at values related to the instantaneous voltage potential at the accessed test site whereby the accessed test site provides via photon assisted tunneling through the passivating layer (2) to the conductive overtayer (3) differing values of electron currents as a function of operation voltage differences, and current measurement means (9) is connected to the overlayer (3) to take readings of tunneling electron currents which in turn are a composite function of the laser light excitation of the test sites and the instantaneous voltage at such test sites; whereby the test site accessed by the pulsed taser provides differing readings for proper operation and for faulty operations; and the integrating circuit may be tested without destructive contact probing.
Claim 3
Dependent Claim
52 words
A method according to claim 1, characterised in that bias means (10) is connected to the overlayer (3) of the integrated circuit under test to control the threshold for photon assisted tunneling, whereby the test pad accessed by the pulsed faser provides significantly differing readings for proper oPeration and for faulty operations.
Claim 4
Dependent Claim
22 words
A method according to claim 1 or 2, characterised in that the conductive overlayer (3) is removed after testing has been completed.
Claim 5
Dependent Claim
46 words
A method according to claim 1, 2 or 3, characterised in that the chip-to-test (1) is placed in a mounting (11) having electrical connections (8) complementary to input/output connections of the chip-to-test and supporting the chip-to-test for accessibility by laser photons to the test sites (4).
Claim 6
Dependent Claim
124 words
An integrated circuit process intermediate chip-to-test having a plurality of operational integrated circuits which is arrayed under a passivation layer (2), characterised in that the passivation layer (2) is of a material which is photon transmissive and susceptible for photon-assisted tunneling, that a plurality of conductive test pads (4), is provided associated with circuits to be tested at locations accessible by photons through the passivation layer, and a photon- transparent conductive overtayer (3) is provided over the passivation layer (2) to constitute test output connecting means, wheredby such chip-to-test may be mounted for exercise in a test operational mode, test sites may be laser accessed during exercise, and photon assisted tunneling values related to operational parameters may be taken from the transparent conductive layer.
Claim 7
Dependent Claim
124 words
An integrated circuit process intermediate chip-to-test having a plurality of operational integrated circuits which is arrayed under a passivation layer (2), characterised in that the passivation layer (2) is of a material which is photon transmissive and susceptible for photon-assisted tunneling, that a plurality of conductive test pads (4), is provided associated with circuits to be tested at locations accessible by photons through the passivation layer, and a photon- transparent conductive overtayer (3) is provided over the passivation layer (2) to constitute test output connecting means, wheredby such chip-to-test may be mounted for exercise in a test operational mode, test sites may be laser accessed during exercise, and photon assisted tunneling values related to operational parameters may be taken from the transparent conductive layer.
Claim 8
Dependent Claim
37 words
A chip-to-test according to claim 5, characterised by at least one input-output contact (12) designated for test con- necrion and connections means (13) connecting the test connection contact (12) to the transparent conductive overlayer (3) (FIG. 3).
Claim 9
Dependent Claim
33 words
A chip-to-test according to claim 5 or 6, characterised by a photon-opaque passivation layer (15), in which photon- transparent window openings (14) provide access for laser light to test sites (4) (FIG. 3).
References Cited (Backward Citations)
EP0005762A1
Cited
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