Cache MMU system

Claim 2

In a computer having an addressable primary memory for selectively storing and outputting data responsive to addresses and a processor for outputting data and addresses, an integrated cache memory system comprising: (a) processor interface means, for coupling to the processor, for receiving logical addresses and for selectively coupling digital system information between said processor and the cache memory system; (b) primary memory interface means for coupling to the primary memory, for selectively coupling digital system information between the primary memory and the cache memory system; (c) addressable read-write cache memory for selectively storing and outputting digital system information; (d) tag memory for storing an associative map of addresses corresponding to digital system information presently stored in said cache memory; (e) comparator means, for providing a hit signal responsive to the correspondence of the processor address output to a presently mapped cache memory addressable location, and for providing a miss signal responsive to a determination of a lack of said correspondence; (f) access controller means for selectively coupling a plurality of words of said digital system information, seriatim, between said cache memory and said processor interface means responsive to said hit signal; (g) memory controller means for selectively coupling said digital system information between the primary memory and the cache memory system responsive to a miss signal.

Claim 3

The system as in Claim 1 further characterized in that the primary memory is responsive to physical addresses, and in that the processor outputs logical addresses, said system further comprising: memory management means for providing an output to the primary memory interface the physical address corresponding to the logical address output from the processor, responsive to said miss signal, in accordance with a predetermined logical to physical correspondence translation.

Claim 4

In a computer having an addressable primary memory for selectively storing and outputting data responsive to addresses and a processor. for outputting data and addresses, an integrated cache memory system comprising: (a) processor interface means, for coupling to the processor, for selectively receiving logical addresses and for selectively coupling digital system information between said processor and the cache memory system; (b) interface register means for selectively storing a plurality of words of digital system information for transfer of said information at high speed with said processor interface means; (c) primary memory interface means for coupling to the primary memory, for selectively coupling digital system information between the primary memory and the cache memory system; (d) addressable read-write cache memory for selectively storing and outputting digital system information; (e) tag memory for storing an associative map of addresses corresponding to digital system information presently stored in said cache memory; (f) comparator means, for providing a hit signal responsive to the correspondence of the processor address output to a presently mapped cache memory addressable location, and for providing a miss signal responsive to a determination of a lack of said correspondence; (g) access controller means for selectively transferring a plurality of words of said digital system information between said cache memory and said interface register means for output to said processor interface means responsive to said hit signal; (h) memory controller means for selectively coupling a plurality of words of said digital system information between the primary memory and the cache memory system responsive to a miss signal.

Claim 5

In a computer having an addressable primary memory for selectively storing and outputting data responsive to addresses and a processor. for outputting data and addresses, an integrated cache memory system comprising: (a) processor interface means, for coupling to the processor, for selectively receiving logical addresses and for selectively coupling digital system information between said processor and the cache memory system; (b) interface register means for selectively storing a plurality of words of digital system information for transfer of said information at high speed with said processor interface means; (c) primary memory interface means for coupling to the primary memory, for selectively coupling digital system information between the primary memory and the cache memory system; (d) addressable read-write cache memory for selectively storing and outputting digital system information; (e) tag memory for storing an associative map of addresses corresponding to digital system information presently stored in said cache memory; (f) comparator means, for providing a hit signal responsive to the correspondence of the processor address output to a presently mapped cache memory addressable location, and for providing a miss signal responsive to a determination of a lack of said correspondence; (g) access controller means for selectively transferring a plurality of words of said digital system information between said cache memory and said interface register means for output to said processor interface means responsive to said hit signal; (h) memory controller means for selectively coupling a plurality of words of said digital system information between the primary memory and the cache memory system responsive to a miss signal.

Claim 6

The cache memory system of Claim 3 further comprising: an incrementable program counter for selectively storing and outputting an address received in said digital system information from said processor interface; wherein said access controller means is further comprised of means for transferring said digital system information associated with said address output from said program counter, and means for repetitively incrementing said program counter and outputting the program counter address to provide for the transfer of said plurality of words of said digital system information between said interface register and said processor interface means.

Claim 7

An integrated cache memory management system coupled to a main memory via a system bus and independently coupled to a processor via a processor/cache bus, said cache memory management system comprising: cache memory means for selectively storing data coupled thereto from the main memory and for selectively outputting said stored data to said processor; address translation means for outputting a physical address to the cache memory subsystem responsive to an address as output from the processor; and main memory management means for providing a real address output via the system bus to the main memory as required by the cache memory management system to access and load the cache memory subsystem with data from the main memory.

Claim 8

An integrated cache memory management system coupled to a main memory via a system bus and independently coupled to a processor via a processor/cache bus, said cache memory management system comprising: cache memory means for selectively storing data coupled thereto from the main memory and for selectively outputting said stored data to said processor; address translation means for outputting a physical address to the cache memory subsystem responsive to an address as output from the processor; and main memory management means for providing a real address output via the system bus to the main memory as required by the cache memory management system to access and load the cache memory subsystem with data from the main memory.

Claim 9

The system as in Claim 5 wherein said address translation means is further comprised of a hardwired page translation subsystem for providing nonvolatile virtual to physical address translation.

Claim 10

The system as in Claim 5 wherein the address translation means is responsive to commands received from the processor.

Claim 11

The system as in Claim 5 wherein the address translation means is responsive to commands received from the system bus.

Claim 12

The system as in Claim 5 wherein said cache memory management system is further comprised of means responsive to commands received from the system bus and from the translation logic means to selectively invalidate, read, and write to the cache memory means

Claim 13

The cache system as in Claim 5 further comprising: bus request means coupled to the system bus for generating a bus request output when said cache memory management system requires access to the main memory via the system bus; bus grant means for activating said cache memory subsystem to interact with main memory via the system bus responsive to receiving a bus grant signal; and wherein said cache memory system is coupled to an external bus arbiter system for coupling bus request and bus grant signals therebetween.

Claim 14

The system as in Claim 5 wherein said cache memory means is a two-way set associative memory.

Claim 15

The system as in Claim 5 wherein said address translation means is comprised of a two-way set associative memory.

Claim 16

A cache memory management system coupled to a processor via a processor/cache bus and to a main memory via a system bus, said cache system comprising: processor interface means for coupling data between the cache system and the processor via the processor/cache bus; system bus interface means for coupling data between the cache system and the main memory via the system bus; address translation means for selectively providing a real address output responsive to an externally supplied input address; cache memory means for storing and outputting data in an associative manner responsive to the externally input address and to said real address output of said address translation means, said cache memory means further comprising hit/miss logic for determining the presence of valid data for the requested addressed locations in the cache memory means; and controller means for accessing main memory on cache memory system misses so as to load translation information and data from main memory to the cache.

Claim 17

A cache memory management system coupled to a processor via a processor/cache bus and to a main memory via a system bus, said cache system comprising: processor interface means for coupling data between the cache system and the processor via the processor/cache bus; system bus interface means for coupling data between the cache system and the main memory via the system bus; address translation means for selectively providing a real address output responsive to an externally supplied input address; cache memory means for storing and outputting data in an associative manner responsive to the externally input address and to said real address output of said address translation means, said cache memory means further comprising hit/miss logic for determining the presence of valid data for the requested addressed locations in the cache memory means; and controller means for accessing main memory on cache memory system misses so as to load translation information and data from main memory to the cache.

Claim 18

The system as in Claim 13 wherein said address translation means is further comprised of: a two-way set associate memory system.

Claim 19

The system as in Claim 13 wherein said controller means is further comprised of: a segment table origin address register; direct address translation means comprising means for selectively accessing main memory via the system bus to obtain a page table entry address responsive to the segment table origin address and the processor supplied externally input address; means for selectively accessing main memory via the system bus to obtain page table translation and system information from main memory responsive to said page table entry address and the processor supplied address; means for storing said translation and system information in said address translation means; and means for accessing the main memory via the system bus for transfer of data from the main memory to the cache memory means responsive to said address translation means.

Claim 20

The system as in Claim 15 wherein said system information includes protection level data, and wherein said cache system is further comprised of protection means for selectively limiting cache memory access responsive to said protection level data.

Claim 21

The system as in Claim 15 wherein the system information includes system tag data, and wherein said cache system selectively operates in one of a predefined plurality of modes responsive to said system tag data.

Claim 22

The system as in Claim 17 wherein said modes include write-through/copy-back and cacheable/non-cacheable.

Claim 23

The system as in Claim 13 wherein said cache memory means is further comprised of: a read-write memory array for storing and outputting data in four-word blocks per addressable block; a line register for storing and outputting a four-word block of data corresponding to a currently active requested address; a boundary register for storing the starting address for the block of words currently stored in the line register; boundary detection means for determining when the current requested address corresponds to data stored in the line register; means for selectively outputting a word from the line register to the processor via the processor interface, responsive to the boundary detection means determining correspondence; and means for selectively transferring data for the requested addressed location from the cache memory array to the line registers for output therefrom, further comprising means for loading the boundary register with the respective requested address.