Tri-state buffer circuit

Claim 2

A tri-state buffer circuit comprising: (a) a switchingcircuit (34) connected to an input terminal (IN), tri-state and inverted tri-state input terminals (T, T), and a first power supply terminal for generating first and second switching signals (A, B) which have first and second levels, respectively, only when the tri-state signal is on a first level, regardless the level of the input signal from the input terminal (IN); (b) an inverter circuit(36) connected to said switching circuit (34), and the first power supply terminal for inverting the first switching signal (A) from said switching circuit (34) as an output signal; (c) a selection circuit (38) connected to said switching circuit and inverter circuit for maintaining a signal, which have a second level, equal to the inverted signal only when the tri-state signal is on first level; (d) a first type first bipolar transistor (60) whose base is connected to said inverter circuit (36), whose collector is connected to the first power supply terminal, and whose emitter is connected to the output terminal of the tri-state circuit; and' (e) a first type second bipolar transistor- (62) whose base is connected to said selection circuit (38), whose collecter is connected to the output terminal of the tri-state circuit, and whose emitter is connected to a second power supply terminal.

Claim 3

A tri-state buffer circuit as claimed in claim 1, wherein said inverter circuit (36) has first type (42) and second type (44) MOS transistors each gate of which is connected in parallel to the first output terminal of said switching circuit (34) from which the first switching signal is supplied, each drain of which is connected in parallel to each other as an output terminal thereof, and each source of which is connected to the first and second power supply terminals, respectively.

Claim 4

A tri-state buffer circuit as claimed in claim 3, wherein said selection circuit (38) has a pair of second type MOS transistors (50,'52) each drain of which is connected in parallel to each other as an output terminal, gate of one of which is connected to a tri-state signal input terminal and gate of other of which is connected to the output terminal of said inverter circuit (36), and each source of which is connected to the second power supply terminal, and a second type MOS transistor (54) a drain of which is connected to the output terminal (out) of the tri-state circuit, a gate of which is connected to the second output terminal of said switching circuit (34) from which the second switching signal is supplied, and a source of which is connected to the drains of the second type MOS transistors (50, 52).

Claim 5

A tri-state buffer circuit as claimed in claim 3, wherein the first type MOS transistor (42) of said inverter circuit (36) is P type MOS transistor, the second type MOS transistors (44, 50, 52, 54) of said inverter crcuit (36), and said selection circuit (3&) are N type MOS transistors, and said first and second first type bipolar transistors (60, 62) are NPN bipolar transistors.

Claim 6

A tri-state buffer circuit comprising: (a) a switching circuit (34) having a pair of first type MOS transistors (14, 16) each source of which is connected in parallel to the first power supply terminal, and each drain of which is connected in parallel to each other as the first output terminal, a pair of first and second type MOS transistors (18, 20) each drain and source of which are connected in parallel to the first and second output terminals, and a pair of second type MOS transistors (22, 24) each drain of which is connected in parallel to the second output terminal, and each sourco of which is connected in parallel to the second power supply termnal; the gate of the first type first MOS transistor (14) of the pair of first type MO S transistors (14, 16) and the gate of the second type MOS transistor (18) of the pair of first and second type MOS transistors (18, 20) being connected n parallel to the inverted tri-state termnal (T), the gate of the first type MOS transistor (20) of the pair of first and second type MOS transistors (18, 20) and the gate of the second type second MOS transistor (24) of the pair of second type MOS transistors (22, 24) being connected in parallel to the tri-state termnal (T), and the gate of the first type second MOS transistor (16) of the pair of first type MOS transistors (14, 16) and the gate of the second type first MOS transistor (22) of the pair of second type MOS transistors (22, 24) being connected in parallel to the input terminal (IN): (b) an inverter circuit (36) having first type (42) and second type (44) MOS transistors, each gate of which is connected in parallel to the first output terminal of said switching circuit (34) from which the first switching signal is supplied, each drain of which is connected in parallel to each other as an output terminal thereof, and each source of which is connecLcd to the first and second power supply terminals, respectively; (c) a selection circuit (38) having a pair of second type MOS transistors (50, 52) each drain of which is connected in parallel to each other as an output terminal, gate of one of which is connected to a tri-state signal input terminal and gate of other of which is connected to the output terminal of said inverter circuit (36), and each source of which is connected to the second power supply terminal, and a second type MOS transistor (54) a drain of which is connected to the output terminal (out) of the tri-state circuit, a ground of which is connected to the second output terminal of said switching circuit (34) from which the second switching signal is supplied, and a source of which is connected to the drains of the second type MOS transistors (50, 52); (d) a first type first bipolar transistor (60_) whose base is connected to the output terminal of said inverter circuit (36), whose collecter is connected to the first power supply terminal, and whose emitter is connected to the output terminal of the tri-state circuit; and (e) a first type second bipolar transistor (62) whose base is connected to the output terminal of said selection circuit (38), whose collector is connected to the output terminal, and whose emitter is connected to a second power supply terminal.

Claim 7

A tri-state buffer circuit comprising: (a) a switching circuit (34) having a pair of first type MOS transistors (14, 16) each source of which is connected in parallel to the first power supply terminal, and each drain of which is connected in parallel to each other as the first output terminal, a pair of first and second type MOS transistors (18, 20) each drain and source of which are connected in parallel to the first and second output terminals, and a pair of second type MOS transistors (22, 24) each drain of which is connected in parallel to the second output terminal, and each sourco of which is connected in parallel to the second power supply termnal; the gate of the first type first MOS transistor (14) of the pair of first type MO S transistors (14, 16) and the gate of the second type MOS transistor (18) of the pair of first and second type MOS transistors (18, 20) being connected n parallel to the inverted tri-state termnal (T), the gate of the first type MOS transistor (20) of the pair of first and second type MOS transistors (18, 20) and the gate of the second type second MOS transistor (24) of the pair of second type MOS transistors (22, 24) being connected in parallel to the tri-state termnal (T), and the gate of the first type second MOS transistor (16) of the pair of first type MOS transistors (14, 16) and the gate of the second type first MOS transistor (22) of the pair of second type MOS transistors (22, 24) being connected in parallel to the input terminal (IN): (b) an inverter circuit (36) having first type (42) and second type (44) MOS transistors, each gate of which is connected in parallel to the first output terminal of said switching circuit (34) from which the first switching signal is supplied, each drain of which is connected in parallel to each other as an output terminal thereof, and each source of which is connecLcd to the first and second power supply terminals, respectively; (c) a selection circuit (38) having a pair of second type MOS transistors (50, 52) each drain of which is connected in parallel to each other as an output terminal, gate of one of which is connected to a tri-state signal input terminal and gate of other of which is connected to the output terminal of said inverter circuit (36), and each source of which is connected to the second power supply terminal, and a second type MOS transistor (54) a drain of which is connected to the output terminal (out) of the tri-state circuit, a ground of which is connected to the second output terminal of said switching circuit (34) from which the second switching signal is supplied, and a source of which is connected to the drains of the second type MOS transistors (50, 52); (d) a first type first bipolar transistor (60_) whose base is connected to the output terminal of said inverter circuit (36), whose collecter is connected to the first power supply terminal, and whose emitter is connected to the output terminal of the tri-state circuit; and (e) a first type second bipolar transistor (62) whose base is connected to the output terminal of said selection circuit (38), whose collector is connected to the output terminal, and whose emitter is connected to a second power supply terminal.

Claim 8

A tri-state buffer circuit comprising: (a) a switching circ (34) connected to first and second input terminals (IN 1, IN 2), tri-state and inverted tri-statc input terminals ( T , T), and a first power supply terminal for generating first and second switching signals (A, B) which have first and second levels, respectively, only when the tri-statc signal is on a first level, regardless the levels of the input signals from the first and second input terminals (IN 1, IN 2); (b) an inverter circuit(36) connected to said switching circuit (34), and the first power supply terminal for invcrting the first switching signal (A) from said switching circuit (34) as an output signal; (c) a selection circuit (38) connected to said switching circuit and inverter circuit for maintaining a signal, which has a second level, equal to the inverted signal only when the tri-state signal is on first level; . (d) a first type first bipolar transistor (60) whose base 'is connected to said inverter circuit (36), whose collector is connected to the first power supply terminal, and whose emitter is connected to the output terminal of the tri-state circuit; and (e) a first type second bipolar transister (62) whose base is connected to said selection circuit (38), whose collector is connected to the output terminal of the tri-state circuit, and whose emitter is connected to a second power supply terminal.

Claim 9

A tri-state buffer circuit comprising: (a) a switching circ (34) connected to first and second input terminals (IN 1, IN 2), tri-state and inverted tri-statc input terminals ( T , T), and a first power supply terminal for generating first and second switching signals (A, B) which have first and second levels, respectively, only when the tri-statc signal is on a first level, regardless the levels of the input signals from the first and second input terminals (IN 1, IN 2); (b) an inverter circuit(36) connected to said switching circuit (34), and the first power supply terminal for invcrting the first switching signal (A) from said switching circuit (34) as an output signal; (c) a selection circuit (38) connected to said switching circuit and inverter circuit for maintaining a signal, which has a second level, equal to the inverted signal only when the tri-state signal is on first level; . (d) a first type first bipolar transistor (60) whose base 'is connected to said inverter circuit (36), whose collector is connected to the first power supply terminal, and whose emitter is connected to the output terminal of the tri-state circuit; and (e) a first type second bipolar transister (62) whose base is connected to said selection circuit (38), whose collector is connected to the output terminal of the tri-state circuit, and whose emitter is connected to a second power supply terminal.