EP0196059A2
Expired / Lapsed
EP
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Write clock generator for time base corrector
Assignee: Sony Corp
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Filing: 1986-03-25
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Granted: —
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Expires: 2006-03-25
Abstract
Abstract A write clock generator (2, 10) for a time base corrector incorporated in a video tape recorder can generate a write clock signal (WCK) including accurate phase and frequency fluctuation information on a reproduced video signal (VDIN) in spite of a simple circuit configuration. A write clock signal (WCK) is generated from a VCO (12) which oscillats in response to a reproduced burst signal (BURST). Further the VCO (12) is so controlled on the basis of frequency difference (S21) between said generated write clock signal (WCK) and a frequency fluctuation signal (S19) that the frequency difference (S21) may be eliminated. The frequency fluctuation signal (S19) is generated in response to a horizontal synchronizing signal H (SYNC) so as to include time base fluctuations in a reproduced video signal (VDIN).
Inventors
- 👤 Yoshiyuki Nakamura
- 👤 Tsutomu Takamori
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 09:30
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/79; H04N9/87; H04N9/89; H04N9/896
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
173 words
A write clock generator for a time base corrector for reducing time base fluctuations involved in a reproduced video signal (VDIN), characterized in (a) means (2,10;11) for generating a write clock signal (WCK) in response to a burst signal (BURST) included in the reproduced video signal (VDIN), an initial phase of the write clock signal (WCK) being synchronized with a phase of the burst signal (BURST); (b) means (2,10;19) for generating a frequency fluctuation signal (S19) in response to a horizontal synchronizing signal H (SYNC) included in the reproduced video signal (VDIN) ; (c) means (13-21,25) for detecting a difference in frequency between the write clock signal (WCK) and the frequency fluctuation signal (S19) and generating a frequency difference signal (S21); and (d) means (12), connected to said write clock signal generating means, for controlling a frequency of the write clock signal (WCK) so that the difference in frequency between the write clock signal (WCK) and the frequency fluctuation signal (S19) is reduced to zero in response to the frequency difference signal (S21).
Claim 2
Dependent Claim
173 words
A write clock generator for a time base corrector for reducing time base fluctuations involved in a reproduced video signal (VDIN), characterized in (a) means (2,10;11) for generating a write clock signal (WCK) in response to a burst signal (BURST) included in the reproduced video signal (VDIN), an initial phase of the write clock signal (WCK) being synchronized with a phase of the burst signal (BURST); (b) means (2,10;19) for generating a frequency fluctuation signal (S19) in response to a horizontal synchronizing signal H (SYNC) included in the reproduced video signal (VDIN) ; (c) means (13-21,25) for detecting a difference in frequency between the write clock signal (WCK) and the frequency fluctuation signal (S19) and generating a frequency difference signal (S21); and (d) means (12), connected to said write clock signal generating means, for controlling a frequency of the write clock signal (WCK) so that the difference in frequency between the write clock signal (WCK) and the frequency fluctuation signal (S19) is reduced to zero in response to the frequency difference signal (S21).
Claim 3
Dependent Claim
48 words
The write clock generator as set forth in claim 1, characterized in that each frequency of the write clock signal (WCK) and the frequency fluctuation signal (S19) is n times (n is an integer) higher than that of a subcarrier frequency (fsc) of the reproduced video signal (VDIN).
Claim 4
Dependent Claim
66 words
The write clock generator as set forth in claim 1 or 2, characterized in that said write clock signal generating means comprises: (a) a start pulse generator (11) for generating a start pulse (START) in response to the burst signal (BURST) and (b) a start-stop voltage controlled oscillator (12) for starting an oscillation of the write clock signal (WCK) in synchronism with the start pulse (START).
Claim 5
Dependent Claim
32 words
The write clock generator as set forth in any one of claims 1 to 3, characterized in that said frequency fluctuation signal (S19) generating means is a phase locked loop circuit (19).
Claim 6
Dependent Claim
135 words
The write clock generator as set forth in any one of claims 1 to 4, characterized in that said frequency difference detecting means comprises: (a) a frequency discriminating circuit (13,14,16) for generating a first discrimination signal having an amplitude varying according to frequency of the write clock signal (WC K ) and a second discrimination signal having an amplitude varying according to frequency of the frequency fluctuation signal (S19), separately; (b) a first holding circuit (17) for holding the first discrimination signal; (c) a second holding circuit (20) for holding the second discrimination signal; and (d) a differential voltage detector (21) for detecting a voltage difference between the first and second discrimination signals, the voltage difference (S21) being applied to said write clock signal frequency controlling means (12) to reduce the voltage difference to zero.
Claim 7
Dependent Claim
133 words
The write clock generator as set forth in claim 5, characterized in that said frequency discrimination circuit comprises: (a) a first switching circuit (13) connected to said write clock signal (WCK) generating means (11,12) and said frequency fluctuation signal (S19) generating means (19) for supplying the write clock singal (WCK) and the frequency fluctuation signal (S19) alternately for each horizontal synchronization time interval in response to horizontal synchronizing signal H (SYNC); (b) a frequency discriminator (14) connected to said first switching circuit (13) for generating the first and second discrimination signals (S14) alternately; and (c) a second switching circuit (16) connected between said frequency discriminator (14) and said first and second holding circuits (17,20) for supplying the first and second discrimination signals (S14) alternately to said first and second holding circuits (17,20) separately.
Claim 8
Dependent Claim
57 words
The write clock generator as set forth in claim 6, characterized in that said frequency discriminating circuit further comprises a frequency divider (25) connected between said first switching circuit (13) and said frequency discriminator (14) for matching a duty factor of the write clock signal (WCK) with that of the frequency fluctuation signal (S19), or vice versa.
References Cited (Backward Citations)
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