EP0195460A2
Expired / Lapsed
EP
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Integrated circuit semiconductor device having improved isolation region
Assignee: NEC Corp
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Filing: 1986-03-24
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Granted: —
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Expires: 2006-03-24
Abstract
Abstract An integrated circuit semiconductor device having first and second circuit elements isolated by an improved isolation region is disclosed. The isolation region includes first and second thick insulating layers at least partly embedded in a semiconductor substrate of one conductivity and an impurity portion of one conductivity having a higher impurity concentration than that of the substrate, provided between the first and second thick insulating layer such that it is separated from both of the first and second circuit elements.
Inventors
- 👤 Michio Komatsu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 18:50
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/10; H10W10/13; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; Y; Y10; Y10S; Y10S257/00; Y10S257/906
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
186 words
An integrated circuit semiconductor device comprising a semiconductor substrate, a first area of one conductivity type positioned in said substrate, a first circuit element having an impurity region of the opposite conductivity type formed in said first area of said substrate, a second circuit element having an impurity region of the opposite conductivity type formed in said first area of said substrate, and an isolation region for isolating said first and second circuit elements provided between said first and second circuit elements, said isolation region including a first impurity portion of one conductivity type having a higher impurity concentration than that of said first area of said substrate provided in said first area of said substrate separately from both of said first and second circuit elements, a thin insulating film provided on the upper surface of said first impurity portion, a first thick insulating layer at least partly embedded in said substrate and provided on one side of said thin insulating film, and a second thick insulating layer at least partly embedded in said substrate and provided on the other side of said thin insulating film.
Claim 2
Dependent Claim
186 words
An integrated circuit semiconductor device comprising a semiconductor substrate, a first area of one conductivity type positioned in said substrate, a first circuit element having an impurity region of the opposite conductivity type formed in said first area of said substrate, a second circuit element having an impurity region of the opposite conductivity type formed in said first area of said substrate, and an isolation region for isolating said first and second circuit elements provided between said first and second circuit elements, said isolation region including a first impurity portion of one conductivity type having a higher impurity concentration than that of said first area of said substrate provided in said first area of said substrate separately from both of said first and second circuit elements, a thin insulating film provided on the upper surface of said first impurity portion, a first thick insulating layer at least partly embedded in said substrate and provided on one side of said thin insulating film, and a second thick insulating layer at least partly embedded in said substrate and provided on the other side of said thin insulating film.
Claim 3
Dependent Claim
70 words
An integrated circuit semiconductor device of Claim 1 further comprising second and third impurity portions of one conductivity type having an impurity concentration of a value higher than that of said first area of said substrate and lower than that of said first impurity portion, said second impurity portion being provided under said first thick insulating layer and said third impurity portion being provided under said second thick insulating layer.
Claim 4
Dependent Claim
31 words
An integrated circuit semiconductor device of Claim 1, in which said impurity concentration of said first impurity portion ranges from 5 x 10 18 to 1 x 1020 atoms/cm 3 .
Claim 5
Dependent Claim
60 words
An integrated circuit semiconductor device of Claim 2, in which said impurity concentration of said first impurity portion ranges from 5 x 10 18 to 1 x 10 2 0 atoms/cm 3 , and said impurity concentration of said second and impurity portions ranges from 5 x 10 16 to 1 x 10 18 ato ms/c m 3 , respectively.
Claim 6
Dependent Claim
43 words
An integrated circuit semiconductor device of Claim 1 further comprising a second area of the opposite conductivity type positioned in said substrate, and a third circuit element having an impurity region of one conductivity type formed in said second area of said substrate.
Claim 7
Dependent Claim
56 words
An integrated circuit semiconductor device of Claim 1, in which the conductivity type of said first area of said substrate is P-type, and said first and second circuit elements are N-channel type insulated gate field effect transistors, each of said impurity regions of said first and second circuit elements being source, drain regionsof said transistors, respectively.
Claim 8
Dependent Claim
62 words
An integrated circuit semiconductor device of Claim 5, in which the conductivity type of said first area of said substrate is P-type, and the conductivity of said second area of said substrate is N-type, said first and second circuit elements being N-channel type insulated gate field effect transistors, respectively, said third circuit element being a P-channel type insulated gate field effect transistor.
Claim 9
Independent Claim
94 words
A method of manufacturing an integrated circuit semiconductor device comprising the steps of forming first and second thick insulating layer at least partly embedded in a semiconductor substrate of one conductivity type and abutted against a first and a second circuit element areas, respectively, and forming an impurity region of one conductivity type having a higher impurity concentration than that of said substrate by introducing an impurity of one conductivity type into said substrate between said first and second thick insulating layers by using said first and second thick insulating layers as a mask.
Claim 10
Independent Claim
94 words
A method of manufacturing an integrated circuit semiconductor device comprising the steps of forming first and second thick insulating layer at least partly embedded in a semiconductor substrate of one conductivity type and abutted against a first and a second circuit element areas, respectively, and forming an impurity region of one conductivity type having a higher impurity concentration than that of said substrate by introducing an impurity of one conductivity type into said substrate between said first and second thick insulating layers by using said first and second thick insulating layers as a mask.
References Cited (Backward Citations)
No citation records indexed.
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