EP0195245A2
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EP
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A high performance parallel vector processor having a modified vector register/element processor configuration
Assignee: International Business Machines Corp
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Filing: 1986-02-14
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Granted: —
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Expires: 2006-02-14
Abstract
Abstract A parallel vector processor is disclosed. The vector processor comprises a plurality of vector registers, each vector register being subdivided in a plurality of smaller registers. A vector is stored in each vector register, the vector comprising a plurality of elements. The elements of the vectors are assigned for storage in the smaller registers of the vector register. In the parallel vector processor of the present invention, assume that each vector register is sub- divided into M smaller registers. The first successive M elements of an N element vector are assigned for storage in the M smaller registers of the vector register. An element processor is connected to each smaller register. Therefore, the first successive M elements of the N element vector are processed by the element processors 1 through M. The second successive M elements of the N element vector are assigned for storage in the same M smaller registers. The third successive M elements of the N element vector are assigned for storage in the M smaller registers. The second and third successive M elements of the N element vector are each processed by the element processors 1 through M. As a result, if the elements of a vector must be processed sequentially, when a second element, stored in a smaller register, is ready for processing by an element processor, the processing of the second element need not await the completion of the processing of a first element stored in the same vector register.
Inventors
- 👤 Chuck Hong Ngai
- 👤 Gerald Joseph Watkins
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 11:30
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8092; G06F15/8007
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
123 words
A vector processor, comprising: a plurality of vector registers (12(6)), each vector register having elements of a vector stored therein, each vector register being subdivided into a plurality of smaller registers (12a(6)), each of the elements of the vector being assigned for storage in a smaller register of the plurality of smaller registers; a plurality of processor means (20(6)) connected to the plurality of smaller registers (12a(6)) of each of said vector registers, the assignment of an element of a vector for storage in a particular smaller register in a vector register being constrained in order to allow the processing of a second sequential element of the vector to continue to completion while a first element of the vector is still undergoing processing.
Claim 2
Dependent Claim
123 words
A vector processor, comprising: a plurality of vector registers (12(6)), each vector register having elements of a vector stored therein, each vector register being subdivided into a plurality of smaller registers (12a(6)), each of the elements of the vector being assigned for storage in a smaller register of the plurality of smaller registers; a plurality of processor means (20(6)) connected to the plurality of smaller registers (12a(6)) of each of said vector registers, the assignment of an element of a vector for storage in a particular smaller register in a vector register being constrained in order to allow the processing of a second sequential element of the vector to continue to completion while a first element of the vector is still undergoing processing.
Claim 3
Dependent Claim
160 words
A vector processor, comprising: a plurality of vector registers (12(6)) disposed approximately parallel to one another, each vector register storing a vector therein, the vector having N elements, each vector register being subdivided into M smaller registers (12a(6)), where M is the number of smaller registers per vector register, the N element vector being subdivided into a plurality of subgroups, each subgroup having M elements, the M elements associated with each subgroup of an N element vector being stored, respectively, in the M smaller registers of a vector register; and a plurality of element processor means (20(6)) connected, respectively, to the corresponding smaller registers of said plurality of vector registers for processing the elements of the vector stored in said vector registers, each element processor means of said plurality of element processor means being cannected to the corresponding smaller registers of the plurality of vector register means for processing the elements of the vector stored in said corresponding smaller registers.
Claim 4
Dependent Claim
160 words
A vector processor, comprising: a plurality of vector registers (12(6)) disposed approximately parallel to one another, each vector register storing a vector therein, the vector having N elements, each vector register being subdivided into M smaller registers (12a(6)), where M is the number of smaller registers per vector register, the N element vector being subdivided into a plurality of subgroups, each subgroup having M elements, the M elements associated with each subgroup of an N element vector being stored, respectively, in the M smaller registers of a vector register; and a plurality of element processor means (20(6)) connected, respectively, to the corresponding smaller registers of said plurality of vector registers for processing the elements of the vector stored in said vector registers, each element processor means of said plurality of element processor means being cannected to the corresponding smaller registers of the plurality of vector register means for processing the elements of the vector stored in said corresponding smaller registers.
Claim 5
Dependent Claim
33 words
The vector processor of claim 2, wherein the output of each element processor means is tied together at a junction, the junction being connected to the input of each of the vector registers.
Claim 6
Dependent Claim
61 words
The vector processor of claim 3, further comprising: means (22(6), 26(6), 24(6)) connected to the inputs of said element processor means for controlling the selection of one or more of said vector registers, the selection of the one or more of said vector registers controlling the further processing of the elements stored in said one or more of said vector registers.
Claim 7
Dependent Claim
209 words
The vector processor according to claim 2 wherein each of said element processor means comprises: read means (2 0 a) for reading said one or more of the elements of the vector stored in said one of the vector registers and one or more elements of the vector stored in another of said vector registers; register means (20b, 20c) connected to said read means for storing the elements of the vectors read from the vector register means; . pre-shift means (20f) connected to the register means for shifting the operands associated with the elements of one vector to align said operands with the operands associated with the elements of the other vector; operation means (20g) connected to the pre-shift means for processing the one or more elements of the vectors stored in said one and said another of said vector registers; post-shift means 20i connected to the operation means for receiving a set of results from said operation means and shifting the results a predetermined amount in accordance with the number of similar predetermined type of digits in said results; and post operation storage means 20h for storing the set of results, the set of results being passed to one of the plurality of vector registers for storage therein.
References Cited (Backward Citations)
EP0136538A2
Cited
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