EP0195163A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Video converter device
Assignee: Olivetti SpA
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Filing: 1985-11-21
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Granted: —
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Expires: 2005-11-21
Abstract
Abstract A conventional cathode ray tube controller (20) is set up with various parameters determining the display format by loading values into internal registers. Firstly a pointer register is loaded with A0 = 0 to select one of 18 parameter registers which is loaded with A0 = 1. In order to allow operation in a computer designed for a first display format but using software designed for a second display format, when the controller (20) is addressed, the pointer value is stored in a latch (12) as well as being passed by a buffer (16) to the controller (20). When the parameter value is received the buffer (16) is disabled and a ROM (14) is enabled to read out the correct parameter value to the controller (20) in accordance with an address formed from the data bits in the latch (12) and the data bits on the computer bus (10).
Inventors
- 👤 Alessandro Graciotti
- 👤 Herbert Kutscha
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 22:20
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/14; G06F3/153; G09; G09G; G09G5/00; G09G5/22; G09G5/222; G09G5/227; C; C07; C07K; C07K16/00; C07K16/18; G01; G01N; G01N33/00; G01N33/48; G01N33/50; G01N33/53; G01N33/575; G01N33/57525; G01N33/68; G01N33/6893; G09G5/36; G09G5/39; G09G5/391; G01N2800/00; G01N2800/04; Y; Y10; Y10S; Y10S436/00; Y10S436/804; Y10S436/811; Y10S436/815
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
201 words
A device for converting data having first values to data having second values, the data being used for controlling a display controller (20) in a computer, the first and second values corresponding to a first and second sets of respectively of parameters used with first and second types of display, the device being connectable between a computer data bus (10) and a controller data bus (11) passing to the controller (20) a first group of data to select an address within the controller and a second group of data to control a parameter associated with that address, characterised by a storage device (12) coupled to the computer data bus (10) for storing the first group of data, a buffer (16) interposed between the computer data bus (10) and the controller data bus (11) for selectively isolating or coupling those buses, and a memory (14) having first (A8-All) and second (AO-A7) pluralities of address lines, the first plurality of address lines (A8-A11) receiving the data stored in the storage device (12) and the second plurality of address lines (AO-A70 being coupled to the computer data bus (10), the memory (14) providing the second group of data to the controller data bus (11).
Claim 2
Independent Claim
201 words
A device for converting data having first values to data having second values, the data being used for controlling a display controller (20) in a computer, the first and second values corresponding to a first and second sets of respectively of parameters used with first and second types of display, the device being connectable between a computer data bus (10) and a controller data bus (11) passing to the controller (20) a first group of data to select an address within the controller and a second group of data to control a parameter associated with that address, characterised by a storage device (12) coupled to the computer data bus (10) for storing the first group of data, a buffer (16) interposed between the computer data bus (10) and the controller data bus (11) for selectively isolating or coupling those buses, and a memory (14) having first (A8-All) and second (AO-A7) pluralities of address lines, the first plurality of address lines (A8-A11) receiving the data stored in the storage device (12) and the second plurality of address lines (AO-A70 being coupled to the computer data bus (10), the memory (14) providing the second group of data to the controller data bus (11).
Claim 3
Dependent Claim
27 words
A device according to claim 1, characterised by control logic (50) coupled to the buffer (16) and the memory (14) for selectively enabling the buffer and memory.
Claim 4
Dependent Claim
26 words
A device according to claim 2, characterised in that the first group of data and the second group of data are sequentially applied to the controller.
Claim 5
Dependent Claim
95 words
A device according to claim 3, characterised in that the first group of data are loaded by the storage device (12) and stored therein for application to the memory (14) while the second group of data is received by the memory, and the memory (14) includes data organized into a group of tables and lines of data therein, the tables being selected by the first group of data received from the storage device (12) and the lines in the tables being selected by the second group of data received from the computer data bus (10).
Claim 6
Dependent Claim
89 words
A device according to claim 4, characterised in that the display controller (20) is a CRT controller responsive to a register select signal (AO) which is a logical 0 signal when the first group of data is received on the computer data bus (10) to select a register for controlling a display parameter of the controller, and is a logical 1 when the second group of data is received on the computer data bus (10) to enter data in the register selected according to the first plurality of data.
Claim 7
Dependent Claim
26 words
A device according to claim 5, characterised in that the storage device stores a value when the register select signal (AO) is equal to logical 0.
Claim 8
Dependent Claim
117 words
A device according to claim 5 or 6, characterised in that the control logic (50) receives a write signal (W) and the register select signal (AO), and has a first output (51) coupled to the buffer (16) and a second output (53) coupled to the memory (14), the logic being such that, when the write signal (W) is in a first state and the register select signal (AO) is in a first state, the buffer (16) is enabled and the memory (14) is disabled, and, when the write signal (W) is in the first state and the register select signal (AO) is in a second state, the buffer (16) is disabled and the memory (14) is enabled.
Claim 9
Dependent Claim
67 words
A device according to claim 7, characterised in that the control logic (50) comprises a multiplexer (60) having a plurality of inputs (1C0-2C3) coupled to fixed logical zero and fixed logical 1 signals and having outputs (51, 53) coupled to the memory (14) and buffer (16), the multiplexer selecting the signals at the multiplexer inputs for application to the buffer and memory for disabling and enabling them.
Claim 10
Independent Claim
54 words
The device according to any preceding claim, characterised in that the buffer (16) is a bidirectional buffer for selectively permitting the flow of data from the CRT controller (20) to the computer data bus (10) and for permitting the flow of data from the computer data bus to the CRT controller data bus (11).
Claim 11
Dependent Claim
26 words
A device according to claim 7 and claim 9, characterised in that the direction of the bidirectional buffer (16) is controlled by the write signal (W).
References Cited (Backward Citations)
No citation records indexed.
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