Digital electronic inclination gauge

Claim 2

A digital display apparatus for-.use with a gravitational sensor (20) providing pulse signals indicative of the algebraic sign and magnitude of inclination of said sensor with respect to a reference axis, characterised in that it comprises: a) means (28) for providing clock pulses, b) means (24) responsive to differences of pulse widths of sensor signals for deriving a gating pulse representative of said magnitude. c) divider means (30) responsive to the clock pulses and the gating pulse for providing a first digital count signal representative of said magnitude and a predetermined scale factor, d) means (36) responsive to the sensor signals for providing a signal indicative of the sign of inclination, e) up/down counter means (36) responsive to the first digital count signal, and f) up/down gate means (30) responsive to the sensor signals and coupled to the up/down counter means for incrementing or decrementing the counter means in accordance with said signals.

Claim 3

Apparatus according to in claim 1, characterised in that it further comprises digital data storage means (32) for storing correction factor signals representative of an angular displacement of the sensor (20) from the earth's gravity vector and applying the correction factor signals to the counter means, and means for providing further correction factor signals to the digital store means and for providing further digital count signals representative of the angular difference between said angular displacement and the sensor inclination to a digital display (40).

Claim 4

Apparatus according to claim 2, characterised in that it further comprises display driver means (14) coupled to receive the first and further digital count signals and the sign signal for providing said signals to the digital display (40).

Claim 5

Apparatus according to any of the preceding claims, characterised in that it further comprises: a) switch means (46) for providing a control pulse for selecting a desired one of a plurality of scale factors, b) oscillator means (Xl) for generating the clock pulses at a frequency representative of the selected scale factor, c) first and second divider means (208,210) responsive to the clock pulses, the gating pulse, and the control pulse for providing first and second digital count signals in accordance with ones of said plurality of scale factors. d) latch means (218) responsive to the switch means (46) for selectively and sequentially addressing the first and second divider means, and e) logic gate means (234), responsive to the first and second digital count signals, for providing one of said signals in accordance with the control pulse.

Claim 6

Apparatus according to claim 4, characterised in that a) the first divider means (208) is adapted for scaling the clock pulse to a first predetermined divisor, and for providing the first digital count signal in accordance therewith, and b) the second divider means (210) is adapted to scaling the digital count signal to a second predetermined divisor and for providing the second digital count signal in accordance therewith.

Claim 7

Apparatus according to claim 5, characterised in that the means for deriving a gating pulse comprises exclusive OR logic gate means (212) having first and second inputs coupled to receive first and second pulse signals, respectively, from the sensor (20), the gate means providing a logic high signal of duration proportional to differences in pulse widths of said first and second signals, and inverter means (214) for converting the logic high signal to a logic low signal.

Claim 8

Apparatus according to claim 5 or 6, characterised in that the first divider means (208) comprises binary divider means having a first input for reception of the gating pulse, a second input for reception of the clock pulses, means for counting the clock pulses, and means for providing an output pulse representative of a predetermined fraction of a number of the clock pulses to provide the first digital count signal.

Claim 9

Apparatus according to any of claims 5 to 7, characterised in that the second divider means (210) provides a pluarlity of outputs, corresponding to fractions of the number of clock pulses, gate means (228) for combining at least two of said outputs, and means responsive to a signal from the gate means for selecting one of said fractions to provide the second digital count signal.

Claim 10

Apparatus according to any of claims 5 to 8, characterised in that it further comprises: a) means (508,R7,C7) for providing a pulse of a first predetermined duration representing a maximum allowable inclination in a first direction, b) means (510,R8, C 8) for providing a pulse of a second predetermined duration representing a maximum allowable inclination in an opposing direction, c) logic switch means (516,518) for receiving and comparing the pulses of said first and second duration with the sensor pulses and for deriving a first overrange signal when one of the sensor pulses has a duration greater than the pulse of first duration, and for deriving a second overrange signal when one of the sensor pulses has a duration less than the pulse of second duration, and d) logic gate means (520,522) for coupling one of said first and second overrange signals to the digital display (40) for indicating an overrange condition.

Claim 11

Apparatus according to claim 9, characterised in that the first pulse means comprises a first monostable multivibrator (508) including timing means ( R 7,C7) for establishing the first predetermined duration, the second pulse means comprises a second monostable multivibrator (510) including further timing means (R8,C8) for establishing the second predetermined duration, the multivibrator receiving a trigger signal for synchronising the first and second pulses with said sensor pulses.

Claim 12

Apparatus according to claim 9 or 10 characterised in that the logic switch means comprises first and second type D bistable multivibrators (516,518), respectively coupled to receive one of the first and second pulses of predetermined duration and connected to receive at least portions of the sensor pulses, the multivibrators (516,518) being biased so that the associated timing means (R7,C7;R8,C8) provides a clock signal and the sensor pulses provide a.data signal, with the first and second bistable multivibrators providing output signals responsive to the data signal associated therewith when the clock signal actuates the multivibrators, the output signals comprising said overrange signals.

Claim 13

Apparatus according to claim 11 characterised in that the logic gate means comprises OR gate means (520), having a first input coupled to receive output signals from the first bistable multivibrator (516) and a second input coupled to receive output signals from the second bistable multivibrator (518), for providing an output indicative of an overrange condition when one of the bistable multivibrators (516,518) is activated.

Claim 14

Apparatus according to any of the preceding claims, characterised in that it further comprises: a) digital timing circuit means (100) for generating a plurality of synchronous timing pulses, b) AND logic gate means (118) for combining ones of said pulses to provide further clock pulses in accordance with a predetermined time interval representative of a desired update rate signal for the display (40), c) circuit means (51,128) for generating a control pulse to inhibit the update rate signal and maintain an existing digital count on the display, d) OR logic gate means (126) responsive to the control pulse and further ones of the timing pulses for providing a reset signal when energised by at least one of the control or further timing pulses, and e) latch means (130) responsive to the further clock pulse and the reset signal, for providing the update rate signal synchronous with the clock pulse when energised by the further timing pulses, and for inhibiting the update rate signal when energised by the control pulse, the update rate signal being applied to display drive means (34).

Claim 15

Apparatus according to claim 13, characterised in that the circuit means comprises momentary switch contact means (51), coupled to a source of dc potential and a phase inverter (128) responsive to impulses from the switch means, for providing a logic high output signal when the switch is deactivated and a logic low output signal when the switch contact means is energised with said dc potential, b) the logic gate means (118) having a first input coupled to receive the phase inverter output signals and a second input coupled to receive the timing signals, so as to provide a logic high output signal when energised by a logic high signal at at least one of said first and second inputs, and c) the latch means comprises a type D bistable multivibrator, having a clock input coupled to receive the further clock pulses and a reset input coupled to receive the timing signals, biased to provide a logic high output signal when activated by the clock signal, and a logic low signal when deactivated by a logic high signal from the gate means, so that the latch provides a logic low signal so long as the switch means is engaged with the dc potential, and is responsive to the further clock pulses and the reset signals when the switch means is disengaged.

Claim 16

Apparatus according to any of the preceding claims, characterised in that the sensor signals comprise first and second pulse widths (PW1,PW2), the first pulse width (PWl) has a duration exceeding the second pulse width (PW2) when the sensor (20) has a positive inclination with respect to an earth's gravity vector, the first pulse width (PWl) has a duration less than the second pulse width (PW2) when the sensor (20) has a negative inclination, and in that the apparatus further comprises logic latch means (432) responsive to the sensor signals for comparing the pulse widths and providing an output signal indicative of the algebraic sign of said inclination.

Claim 17

Apparatus according to claim 15, characterised in that it further comprises: a) further latch means (434) responsive to the sensor signals and to signals derived from the update rate signal corresponding to the correction factor signals, for providing a first output signal representative of the algebraic sign of the correction factor signals and a second output signal representative of the inverse algebraic sign thereof, b) comparator means (436) for receiving said first output signal and the sign output signal and providing output signals representative of differences and identity of the algebraic signs of the received signals, c) first multiplexer means (446) for receiving said inverse sign signal and signals derived from the sign output signal responsive to control signals from the up/down counter means (36) and from mode selection means (46), for selectively providing one of the derived sign output signals and the derived inverse sign signal in response to the control signals, thereby to activate an algebraic legend disposed on the digital display (40), and d) second multiplexer means (444), coupled to receive the control signals applied to the first multiplexer means (446), responsive to a signal derived from the output signal of the comparator means (476) and to a signal derived from a source of dc potential, for selectively providing one of said derived signals applied thereto to increment or decrement the up/down counter means (36) in response to the control signals, where by the control signals are representative of operational modes of the apparatus.

Claim 18

Apparatus according to claim 16, characterised in that the operational modes are comprised of a normal, a set offset, and an offset mode.

Claim 19

Apparatus: according to claim 17, characterised in that the operational modes are determined by the mode selection means comprised of-momentary contact switch means (53) coupled to a source of dc potential, bistable multivibrator means (416) responsive to impulses from the switch means, for providing logic state signals to programmable counter means (418), the counter means (418) providing further logic state signals corresponding to sequential impulses from the switch means representative of the operational modes, the further logic signals being applied to control the first and second multiplexers (446,444).

Claim 20

Apparatus according to any of claims 16 to 18, characterised in that the up/down counter means comprises a plurality of cascaded digital counters, (308,310,312,314) each having an input coupled to receive said first digital count signal in serial form, and providing an output signal representative of the count signal in binary form coupled to the digital data storage means (32) for storing the count signal in binary form, the stored count signal being applied to further inputs of the counter means to bias the counter signal in accordance with the derived signals from the second multiplexer (444), means being provided for receiving the derived signals from the second multiplexer, thereby to increment or decrement said output in accordance with said signals and the stored count signal.

Claim 21

Apparatus according to claim 19, characterised in that the control signal from the up/down counter means (36) is provided by OR gate logic means, coupled to receive the count signal in binary form, and responsive to binary digits of the count signal, the OR gate providing a logic high when energised by a binary digit and a logic low when all digits are a null, the output signal from the OR gate means being representative of a logic state thereof and being applied to bistable multivibrator means coupled to provide the control signal corresponding to said logic state to the first and second multiplexer means (446,.444).

Claim 22

Apparatus according to claim 20, characterised in that it further comprises further multiplexer means (302), comprised of a plurality of cascaded multiplexers (316,318,320) and having a first input coupled to receive the count signal in binary form, a second input coupled to a source of d.c. potential for providing a logic high signal thereto, a third input for receiving a signal indicative of the overrange condition, an output for receiving signals selectively coupled from the first or second inputs, means responsive to the overrange signal for coupling the logic high signal to said output, and f) means for coupling the count signal to said output.

Claim 23

Apparatus according to claim 21, characterised in that it further comprises decoder/drive means (304) coupled to receive signals from the further multiplexer means (302) indicative of the magnitude of inclination.

Claim 24

A differential pulse width discriminator characterised in that it comprises: a) a pulse generator for supplying reference pulses of predetermined pulse duration, b) means for applying a pulsed signal, c) means for synchronising the reference pulses and the pulsed signal, d) bistable multivibrator means having a data input for receiving the pulsed signal, a clock input for receiving the reference pulses, and an output responsive thereto, such that the output is indicative of the logic state of a signal applied to the data input when the clock signal undergoes a logic level transition.

Claim 25

A differential pulse width discriminator characterised in that it comprises: a) a pulse generator for supplying reference pulses of predetermined pulse duration, b) means for applying a pulsed signal, c) means for synchronising the reference pulses and the pulsed signal, d) bistable multivibrator means having a data input for receiving the pulsed signal, a clock input for receiving the reference pulses, and an output responsive thereto, such that the output is indicative of the logic state of a signal applied to the data input when the clock signal undergoes a logic level transition.

Claim 26

A discriminator according to in claim 24,. characterised in that the pulse generator comprises a monostable multivibrator.

Claim 27

A discriminator. according to claim 24, characterised in that the bistable multivibrator means comprises a type D flip-flop.