EP0193305A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
System interface for coupling standard microprocessor to a communications adapter
Assignee: Texas Instruments Inc
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Filing: 1986-02-12
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Granted: —
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Expires: 2006-02-12
Abstract
Abstract A communications system of the token-passing, closed- loop type for use as a local area network employs an adapter at each station for coupling a hose processor to a one-way signal path. The host processor includes a host CPU, a main memory, and a system bus. The adapter is coupled to the main memory by the system bus, and includes a local CPU, a local read/write memory, and a local bus. To transmit a message from one station to another, a frame of data is created in the main memory by the hose CPU, and this frame is copied into the local read/write memory by way of the system and local bus, when initiated by the hose CPU. A transmit/receive handler is coupled to the local bus to directly access the local read/write memory. When this station has access to the loop, i.e., receives a free token, the transmit/receive handler copies the message frame from the local read/write memory to the outgoing signal path, via a transmit stack, converting from parallel to serial. When the adapter receives a message addressed to this station, it is converted from serial to parallel, and copied into the local read/write memory via a receive stack and the local bus, interrupting the local CPU. The message frame is then copied from the local.read/write memory to the main memory via the system interface. The local CPU executes instructions fetched from a ROM accessed by the local bus, so the instruction fetch for the local CPU, the direct memory access from the transmit/receive handler for transmitting or receiving data frames, and the access from the hose CPU for copying transmitted or received message frames, all contend for the local bus, using bus arbitration with appropriate priorities.
Inventors
- 👤 Jerry R. Vanaken
- 👤 Carrell R. Killebrew
- 👤 Michael W. Patrick
- 👤 Donald M. Walters
- 👤 Brian K. Shore
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 06:13
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385; G06F13/10; G06F13/12; G06F13/124; G06F13/128; H; H04; H04L; H04L12/00; H04L12/28; H04L12/42; H04L12/427; H04L12/433
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
286 words
1 . A digital data communications system comprising: a) a signal path, b) a plurality of stations connected to said signal path, each station receiving digital data from the path and transmitting digital data to said path, each said station comprising: I) a main processor containing a main CPU, a main memory, and peripheral I/O devices, and having a system bus interconnecting said CPU, main memory, and peripheral I/O devices; the system bus including address/data bus means and a control bus; ii) a communications processor containing a local CPU, a read-only memory, and a local read-write memory; said communications processor having a local multiplexed address/data bus and a local control bus interconnecting said local CPU, read-only memory, and local read/write memory; iii) system interface means connecting said system bus to said local address/data bus and said local control bus whereby said main CPU initiates direct memory access to said local read/write memory and said local CPU initiates direct memory access to said main memory, each said direct memory access being under control of said system interface means, iv) transmit/receive handler means having a data input coupled to said signal path and an output coupled via a receive buffer memory and said local bus to said local read/write memory, and having a data output coupled to said signal path and an input coupled via a transmit buffer memory and said local bus to said local read/write memory, said transmit/receive handler means responsive to initiation by transmit/receive control means to directly access said local r ead/write memory for writing received data from the receive buffer memory to the local read/write memory and reading transmit data from the local read/write memory to the tran 5 mit/receive bus buffer memory.
Claim 2
Dependent Claim
286 words
1 . A digital data communications system comprising: a) a signal path, b) a plurality of stations connected to said signal path, each station receiving digital data from the path and transmitting digital data to said path, each said station comprising: I) a main processor containing a main CPU, a main memory, and peripheral I/O devices, and having a system bus interconnecting said CPU, main memory, and peripheral I/O devices; the system bus including address/data bus means and a control bus; ii) a communications processor containing a local CPU, a read-only memory, and a local read-write memory; said communications processor having a local multiplexed address/data bus and a local control bus interconnecting said local CPU, read-only memory, and local read/write memory; iii) system interface means connecting said system bus to said local address/data bus and said local control bus whereby said main CPU initiates direct memory access to said local read/write memory and said local CPU initiates direct memory access to said main memory, each said direct memory access being under control of said system interface means, iv) transmit/receive handler means having a data input coupled to said signal path and an output coupled via a receive buffer memory and said local bus to said local read/write memory, and having a data output coupled to said signal path and an input coupled via a transmit buffer memory and said local bus to said local read/write memory, said transmit/receive handler means responsive to initiation by transmit/receive control means to directly access said local r ead/write memory for writing received data from the receive buffer memory to the local read/write memory and reading transmit data from the local read/write memory to the tran 5 mit/receive bus buffer memory.
Claim 3
Dependent Claim
37 words
A system according to claim 1 wherein said signal path is a closed, one-way path, and each station receives data from an upstream direction in the path and transmits data to a downstream direction in the path.
Claim 4
Dependent Claim
33 words
A system according to claim 2 wherein said access to said signal path is controlled by a token included in the transmitted data and passed from station to station around the closed path.
Claim 5
Dependent Claim
42 words
A system according to claim 2 wherein data is transmitted on said signal path in bit-serial format, said transmit/receive handler means includes serial-to-parallel conversion means and parallel-to-serial conversion means, and wherein said local bus and system bus each includes a parallel bus.
Claim 6
Dependent Claim
91 words
A system according to claim 4 wherein a frame of a plurality of bytes of data to be transmitted is created in said main memory under control of said main CPU, and such frame is transferred by said system interface means upon Initiation by said main CPU via said system bus and said local bus into said local read/write memory. and subsequently such frame is transferred by said transmit/receive handler means under initiation by said transmit/receive control means via said local bus and said transmit buffer memory to said transmitting means.
Claim 7
Dependent Claim
44 words
A system according to claim 5 wherein said frames of data created in said main memory and transmitted on said signal path by said stations include a destination address identifying a particular one of the stations, and a source address identifying the origination station.
Claim 8
Dependent Claim
37 words
A system according to claim 6 wherein said local CPU executes instructions fetched from said local read-only memory via said local bus, and said main CPU executes instructions fetched from said main memory via said system bus.
Claim 9
Dependent Claim
196 words
A data communications adapter connecting a processor system to a data communications signal path; said processor system having a system CPU, a system memory, a system control bus, and a system address/data bus; said adapter comprising: a) a programmable processor device having a local CPU, a local memory, a local control bus, and a local multiplexed address/data bus connecting the local CPU and local memory; said local memory including read-only memory for storing program instructions executed by said local CPU and including read/write memory for temporarily storing message data; b) a system interface device coupling said local address/data bus to said system address/data bus for transferring message data between said system memory and said local memory by direct memory access in both directions; the system interface device having inputs connected to said system control bus and to said,local control bus; c) a data communications interface device coupling said local bus to said signal path for transferring data between said signal path and said local memory by direct memory access in both directions; d) wherein said data communications interface device, said system interface device, and said local CPU all contend for control of said local address/data bus.
Claim 10
Dependent Claim
196 words
A data communications adapter connecting a processor system to a data communications signal path; said processor system having a system CPU, a system memory, a system control bus, and a system address/data bus; said adapter comprising: a) a programmable processor device having a local CPU, a local memory, a local control bus, and a local multiplexed address/data bus connecting the local CPU and local memory; said local memory including read-only memory for storing program instructions executed by said local CPU and including read/write memory for temporarily storing message data; b) a system interface device coupling said local address/data bus to said system address/data bus for transferring message data between said system memory and said local memory by direct memory access in both directions; the system interface device having inputs connected to said system control bus and to said,local control bus; c) a data communications interface device coupling said local bus to said signal path for transferring data between said signal path and said local memory by direct memory access in both directions; d) wherein said data communications interface device, said system interface device, and said local CPU all contend for control of said local address/data bus.
Claim 11
Dependent Claim
71 words
An adapter according to claim 8 wherein said system interface device contains a memory-mapped I/O channel by which said system CPU accesses said local memory to transfer command and status information, and contains a direct memory access channel by which data is transferred between the system memory and the local memory under control of the system interface device after initiation of the transfer by the system CPU or the local CPU.
Claim 12
Dependent Claim
54 words
An adapter according to claim 8 wherein said data communications Interface device includes a direct memory access channel by which data is transferred between said signal path and said local memory under control of the data communication interface device after initiation of the transfer by the local CPU or the data communications interface device.
Claim 13
Dependent Claim
57 words
An adapter according to claim 8 wherein said programmable processor device includes bus arbitration means to control access to said local bus, and said data communications interface device has highest priority of such access, said system interface device has the next higher priority of such access, and said local CPU has the lower priority of such access.
Claim 14
Dependent Claim
171 words
An adapter according to claim 8 wherein said system interface device contains a memory-mapped I/O channel by which said system CPU accesses said local memory to transfer command and status information, and contains a direct memory access channel by which data is transferred between the system memory and the local memory under control of the system interface device after initiation of the transfer by the system CPU or the local CPU; wherein said data communications interface device includes a direct memory access channel by which data is transferred between said signal path and said local memory under control of the data communication interface device after initiation of the transfer by the local CPU or the data communications interface device; and wherein said programmable processor device includes bus arbitration means to control access to said local bus, and said data communications interface device has highest priority of such access, said system interface device has the next higher priority of such access, and said local CPU has the lower priority of such access.
Claim 15
Dependent Claim
281 words
A digital data communications system comprising: a) a signal path. b) a plurality of stations connected to said signal path each station receiving digital data from the path and transmitting digital data to said path, each said station comprising: i) a main processor containing a main CPU, a main memory, and peripheral I/O devices, and having a system bus interconnecting said CPU, main memory, and peripheral I/O devices; the system bus including address/data bus means and a control bus; ii) a communications processor containing a local CPU, a read-only memory, and a local read-write memory; said communications processor having a local multiplexed address/data bus and a local control bus interconnecting said local CPU, read-only memory, and local read/write memory; iii) system interface means connecting said system bus to said local address/data bus and said local control bus whereby said main CPU initiates direct memory access to said local read/write memory and said local CPU initiates direct memory access to said main memory, each said direct memory access being under control of said system Interface means, iv) transmit/receive handler means having a data input coupled to said signal path and an output coupled via a receive buffer memory and said local bus to said local read/write memory, and having a data output coupled to said signal path and an input coupled via a transmit buffer memory and said local bus to said local read/write memory, said transmit/receive handler means responsive to initiation by transmit/receive control means to directly access said local read/write memory for writing received data from the receive buffer memory to the local read/write memory and reading transmit data from the local read/write memory to the transmit/receive bus buffer memory.
Claim 16
Dependent Claim
281 words
A digital data communications system comprising: a) a signal path. b) a plurality of stations connected to said signal path each station receiving digital data from the path and transmitting digital data to said path, each said station comprising: i) a main processor containing a main CPU, a main memory, and peripheral I/O devices, and having a system bus interconnecting said CPU, main memory, and peripheral I/O devices; the system bus including address/data bus means and a control bus; ii) a communications processor containing a local CPU, a read-only memory, and a local read-write memory; said communications processor having a local multiplexed address/data bus and a local control bus interconnecting said local CPU, read-only memory, and local read/write memory; iii) system interface means connecting said system bus to said local address/data bus and said local control bus whereby said main CPU initiates direct memory access to said local read/write memory and said local CPU initiates direct memory access to said main memory, each said direct memory access being under control of said system Interface means, iv) transmit/receive handler means having a data input coupled to said signal path and an output coupled via a receive buffer memory and said local bus to said local read/write memory, and having a data output coupled to said signal path and an input coupled via a transmit buffer memory and said local bus to said local read/write memory, said transmit/receive handler means responsive to initiation by transmit/receive control means to directly access said local read/write memory for writing received data from the receive buffer memory to the local read/write memory and reading transmit data from the local read/write memory to the transmit/receive bus buffer memory.
Claim 17
Dependent Claim
37 words
A system according to claim 13 wherein said signal path is a closed, one-way path, and each station receives data from an upstream direction in the path and transmits data to a downstream direction in the path.
Claim 18
Dependent Claim
33 words
A system according to claim 14 wherein said access to said signal path is controlled by a token included in the transmitted data and passed from station to station around the closed path.
Claim 19
Dependent Claim
42 words
A system according to claim 15 wherein data is transmitted on said signal path in bit-serial format, said transmit/receive handler means includes serial-to-parallel conversion means and parallel-to-serial conversion means, and wherein said local bus and system bus each includes a parallel bus.
Claim 20
Independent Claim
90 words
A system according to claim 16wherein a frame of a plurality of bytes of data to be transmitted is created in said main memory under control of said main CPU, and such frame is transferred by said system interface means upon initiation by said main CPU via said system bus and said local bus into said local read/write memory, and subsequently such frame is transferred by said transmit/receive handler means under initiation by said transmit/receive control means via said local bus and said transmit buffer memory to said transmitting means.
Claim 21
Independent Claim
43 words
A system according to claim 17wherein said frames of data created in said main memory and transmitted on said signal path by said stations include a destination address identifying a particular one of the stations, and a source address identifying the origination station.
Claim 22
Dependent Claim
37 words
A system according to claim 18 wherein said local CPU executes instructions fetched from said local read-only memory via said local bus, and said main CPU executes instructions fetched from said main memory via said system bus.
Claim 23
Dependent Claim
197 words
A data communications adapter connecting a processor system to a data communications signal path; said processor system having a system CPU, a system memory, a system control bus, and a system address/data bus; said adapter comprising: a) a programmable processor device having a local CPU, a local memory, a local control bus, and a local multiplexed address/data bus connecting the local CPU and local memory; said local memory Including read-only memory for storing program instructions executed by said local CPU and including read/write memory for temporarily storing message data; b) a system interface device coupling said local address/data bus to said system address/data bus for transferring message data between said system memory and said local memory by direct memory access in both directions; the system Interface device having Inputs connected to said system control bus and to said local control bus; c) a data communications interface device coupling said local bus to said signal path for transferring data between said signal path and said local memory by direct memory access In both directions; d) wherein said data communications interface device, said system interface device, and said local CPU all contend for control of said local address/data bus.
Claim 24
Dependent Claim
197 words
A data communications adapter connecting a processor system to a data communications signal path; said processor system having a system CPU, a system memory, a system control bus, and a system address/data bus; said adapter comprising: a) a programmable processor device having a local CPU, a local memory, a local control bus, and a local multiplexed address/data bus connecting the local CPU and local memory; said local memory Including read-only memory for storing program instructions executed by said local CPU and including read/write memory for temporarily storing message data; b) a system interface device coupling said local address/data bus to said system address/data bus for transferring message data between said system memory and said local memory by direct memory access in both directions; the system Interface device having Inputs connected to said system control bus and to said local control bus; c) a data communications interface device coupling said local bus to said signal path for transferring data between said signal path and said local memory by direct memory access In both directions; d) wherein said data communications interface device, said system interface device, and said local CPU all contend for control of said local address/data bus.
Claim 25
Dependent Claim
72 words
21 An adapter according to claim 20 wherein said system interface device contains a memory-mapped I/O channel by which said system CPU accesses said local memory to transfer command and status information, and contains a direct memory access channel by which data is transferred between the system memory and the local memory under control of the system interface device after initiation of the transfer by the system CPU or the local CPU.
Claim 26
Dependent Claim
53 words
An adapter according to claim 21wherein said data communications interface device includes a direct memory access channel by which data is transferred between said signal path and said local memory under control of the data communication interface device after initiation of the transfer by the local CPU or the data communications interface device.
Claim 27
Dependent Claim
57 words
An adapter according to claim 21 wherein said programmable processor device includes bus arbitration means to control access to said local bus, and said data communications interface device has highest priority of such access, said system interface device has the next higher priority of such access, and said local CPU has the lower priority of such access.
Claim 28
Dependent Claim
171 words
An adapter according to claim 21 wherein said system interface device contains a memory-mapped I/O channel by which said system CPU accesses said local memory to transfer command and status information, and contains a direct memory access channel by which data is transferred between the system memory and the local memory under control of the system interface device after initiation of the transfer by the system CPU or the local CPU; wherein said data communications interface device includes a direct memory access channel by which data is transferred between said signal path and said local memory under control of the data communiction interface device after initiation of the transfer by the local CPU or the data communications interface device; and wherein said programmable processor device includes bus arbitration means to control access to said local bus, and said data communications interface device has highest priority of such access, said system interface device has the next higher priority of such access, and said local CPU has the lower priority of such access.
Claim 29
Dependent Claim
287 words
A digital data communications system comprising: a) a signal path, b) a plurality of stations connected to said signal path, each station receiving digital data from the path and transmitting digital data to said path, each said station comprising: i) a main processor containing a main CPU, a main memory, and having a system bus interconnecting said main CPU. and main memory; ii) a communications processor containing a local CPU, a read-only memory, and a local read-write memory; said communications processor having a local multiplexed address/data bus and a local control bus interconnecting said local CPU, read-only memory, and local read/write memory; iii) system interface means connecting said system bus to said local address/data bus and said local control bus whereby said main CPU initiates direct memory access to said local read/write memory and said local CP U initiates direct memory access to said main memory, each said direct memory access being under control of said system interface means, iv) transmit/receive handler means having receive input means coupled to said signal path and to a receive buffer memory, and having a transmit output coupled to said signal path and to a transmit buffer memory; the transmit/receive handler having control means responsive to receipt of data from said signal path at said receive Input; and address and data bus means in said transmit/receive handler means connected to transfer data between said transmit and receive buffer memories and to said local bus means, and means responsive to initiation by said transmit/receive control means to directly access said local read/write memory for writing received data from the receive buffer memory to the local read/write memory and reading transmit data from the local read/write memory to the transmit/recefve bus buffer memory.
Claim 30
Dependent Claim
287 words
A digital data communications system comprising: a) a signal path, b) a plurality of stations connected to said signal path, each station receiving digital data from the path and transmitting digital data to said path, each said station comprising: i) a main processor containing a main CPU, a main memory, and having a system bus interconnecting said main CPU. and main memory; ii) a communications processor containing a local CPU, a read-only memory, and a local read-write memory; said communications processor having a local multiplexed address/data bus and a local control bus interconnecting said local CPU, read-only memory, and local read/write memory; iii) system interface means connecting said system bus to said local address/data bus and said local control bus whereby said main CPU initiates direct memory access to said local read/write memory and said local CP U initiates direct memory access to said main memory, each said direct memory access being under control of said system interface means, iv) transmit/receive handler means having receive input means coupled to said signal path and to a receive buffer memory, and having a transmit output coupled to said signal path and to a transmit buffer memory; the transmit/receive handler having control means responsive to receipt of data from said signal path at said receive Input; and address and data bus means in said transmit/receive handler means connected to transfer data between said transmit and receive buffer memories and to said local bus means, and means responsive to initiation by said transmit/receive control means to directly access said local read/write memory for writing received data from the receive buffer memory to the local read/write memory and reading transmit data from the local read/write memory to the transmit/recefve bus buffer memory.
Claim 31
Dependent Claim
37 words
A system according to claim 25 wherein said signal path is a closed, one-way path, and each station receives data from an upstream direction in the path and transmits data to a downstream direction in the path.
Claim 32
Dependent Claim
33 words
A system according to claim 26 wherein said access to said signal path is controlled by a token included in the transmitted data and passed from station to station around the closed path.
Claim 33
Dependent Claim
49 words
28 . A system according to claim 27 wherein data is transmitted on said signal path in bit-serial format, said receive Input means includes serlal-to-parallel conversion means, said transmit output means includes parallel-to-serial conversion means, and wherein said local bus and system bus each includes a parallel data bus.
Claim 34
Dependent Claim
96 words
29 . A system according to claim 28 wherein a frame of a plurality of bytes of data to be transmitted is created in said main memory under control of said main CPU, and such frame is transferred by said first eccess means upon initiation by said main CPU via said system bus and said local bus into said local read/write memory, and subsequently such frame is transferred by said transmit output means under initiation by said transmit/receive control means via said local bus, and said data bus transmit buffer memory to said transmit output means.
Claim 35
Independent Claim
43 words
A system according to claim 29wherein said frames of data created In said main memory and transmitted on said signal path by said stations Include a destination address identifying a particular one of the stations, and a source address Identifying the origination station.
Claim 36
Dependent Claim
37 words
A system according to claim 80 wherein said local CPU executes instructions fetched from said local read-onty memory via said local bus, and said main CPU executes instructions fetched from said main memory via said system bus.
Claim 37
Dependent Claim
206 words
A data communications adapter connecting a processor system to a data communications signal path; said processor system having a system CPU, a system memory, a system control bus, and a system address/data bus; said adapter comprising: a) a programmable processor device having a local CPU, a local memory, and local address/data bus means connecting the local CPU and local memory; said local memory including read-only memory for storing program instructions executed by said local CPU and including read/write memory for temporarily storing message data; b) a system interface device coupling said local address/data bus to said system address/data bus for transferring message data between said system memory and said local memory by direct memory access in both directions; c) a transmit/receive handler device coupling said local bus means to said signal path for transferring data from said signal path to said local memory by direct memory access, and transferring data from said local memory to said signal path by direct memory access; the transmit/receive handler means Including an address bus, a data bus, a receive buffer memory and a transmit buffer memory; d) wherein said data communications interface device, said system interface device, and said local CPU all contend for control of said local address/data bus.
Claim 38
Dependent Claim
206 words
A data communications adapter connecting a processor system to a data communications signal path; said processor system having a system CPU, a system memory, a system control bus, and a system address/data bus; said adapter comprising: a) a programmable processor device having a local CPU, a local memory, and local address/data bus means connecting the local CPU and local memory; said local memory including read-only memory for storing program instructions executed by said local CPU and including read/write memory for temporarily storing message data; b) a system interface device coupling said local address/data bus to said system address/data bus for transferring message data between said system memory and said local memory by direct memory access in both directions; c) a transmit/receive handler device coupling said local bus means to said signal path for transferring data from said signal path to said local memory by direct memory access, and transferring data from said local memory to said signal path by direct memory access; the transmit/receive handler means Including an address bus, a data bus, a receive buffer memory and a transmit buffer memory; d) wherein said data communications interface device, said system interface device, and said local CPU all contend for control of said local address/data bus.
Claim 39
Dependent Claim
73 words
33 . An adapter according to claim 32 wherein said system interface device contains a memory-mapped I/O channel by which said system CPU accesses said local memory to transfer command and status information, and contains a direct memory access channel by which data is transferred between the system memory and the local memory under control of the system interface device after initiation of the transfer by the system CPU or the local CPU.
Claim 40
Dependent Claim
58 words
An adapter according to claim 33wherein said transmit/receive handler device includes a direct memory access channel by which data is transferred between said signal path and said local memory via said receive buffer memory and said data bus under control of the handler device after initiation of the transfer by the local CPU or by the handler device.
Claim 41
Dependent Claim
56 words
An adapter according to claim 33 wherein said programmable processor device includes bus arbitration means to control access to said local bus, and said transmit/receive handler device has highest priority of such access, said system interface device has the next higher priority of such access, and said local CPU has the lower priority of such access.
Claim 42
Dependent Claim
176 words
36 . An adapter according to claim 33 wherein said system Interface device contains a memory-mapped I/O channel by which said system CPU accesses said local memory to transfer command and status information, and contains a direct memory access channel by which data is transferred between the system memory and the local -memory under control of the system interface device after initiation of the transfer by the system CPU or the local CPU; wherein said transmit/receive handler device includes a direct memory access channel by which data is transferred between said signal path and said local memory via said receive data buffer and said data bus under control of the handler device after Initiation of the transfer by the local CPU or by the handler device: and wherein said programmable processor device includes bus arbitration means to control access to said local bus, and said handler device has highest priority of such access, said system interface device has the next higher priority of such access, and said local CPU has the lower priority of such access.
References Cited (Backward Citations)
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