Patent US6753910B1 successfully refreshed from Google Patents.
EP0193172A2
Expired / Lapsed
EP
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Vertical MOS transistor with peripheral circuit
Assignee: Nissan Motor Co Ltd
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Filing: 1986-02-25
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Granted: —
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Expires: 2006-02-25
Abstract
Abstract An improved semiconductor device having a vertical MOS and another MOS circuit such as C-MOS is shown. To insulate the circuit from influences from the operation of the vertical MOS, the vertical MOS is fabricated in a diffused region which is formed on a semiconductor substrate while the circuit is fabricated in an epitaxial layer of an opposite conductivity type to that of the substrate.
Inventors
- 👤 Tsutomu Matsushita
- 👤 Koichi Murakami
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 22:18
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0195; H10D84/02; H10D84/03; H10D84/038; H10D84/837; H10D84/839; H10W; H10W15/00; H10W15/01
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
149 words
A semiconductor device comprising a substrate (1) of a first conductivity type; an eptaxial layer (25) of a second conductivity type opposite to the first conductivity type; a drain diffused region (7) of the first conductivity type extending from the surface of the eptaxial layer (25) to a depth at which it is in contact with the substrate; a channel region (9) and a source region (11) which are formed in the drain diffused region (7); gate and source electrodes (17, 19) in contact with the channel and source regions (9, 11) respectively; a drain electrode (18) in contact with the substrate, said three region, three electrodes and substrate constituting a vertical MOS transistor (3) jointly; a circuit (5) fabricated on the epitaxial layer (25), which is electrically isolated from the vertical transistor (3) during operation by a reverse bias between the substrate (1) and the epitaxial layer (25).
Claim 2
Dependent Claim
149 words
A semiconductor device comprising a substrate (1) of a first conductivity type; an eptaxial layer (25) of a second conductivity type opposite to the first conductivity type; a drain diffused region (7) of the first conductivity type extending from the surface of the eptaxial layer (25) to a depth at which it is in contact with the substrate; a channel region (9) and a source region (11) which are formed in the drain diffused region (7); gate and source electrodes (17, 19) in contact with the channel and source regions (9, 11) respectively; a drain electrode (18) in contact with the substrate, said three region, three electrodes and substrate constituting a vertical MOS transistor (3) jointly; a circuit (5) fabricated on the epitaxial layer (25), which is electrically isolated from the vertical transistor (3) during operation by a reverse bias between the substrate (1) and the epitaxial layer (25).
Claim 3
Dependent Claim
13 words
A semiconductor device of claim 1, wherein said circuit (5) is a C-MOS.
Claim 4
Dependent Claim
21 words
A semiconductor device of claim 1 further comprising a buried region (40) provided on the bottom of the epitaxial layer (25).
Claim 5
Dependent Claim
16 words
A semiconductor device of claim 3, wherein said buried region (25) is formed by diffusing impurities.
Claim 6
Dependent Claim
40 words
A semiconductor device of claim 1 further comprising a buried region (81) provided on the bottom of the drain diffused region (7), the impurity concentration of the buried region (81) being higher than that of the diffused drain region (7).
Claim 7
Dependent Claim
20 words
A semiconductor device of claim 1, wherein the part of the substrate (1) just below the epitaxial layer is removed.
Claim 8
Dependent Claim
20 words
A semiconductor device of claim 1 further comprising a well region (9) in which said source region (11) is formed.
Claim 9
Dependent Claim
26 words
A semiconductor device of Claim 7, wherein said source electrode (19) is electrically in contact with the well region (9) through a well contact region (13).
Claim 10
Dependent Claim
39 words
A semiconductor device of claim 8, further comprising an intermediate region (81) in contact with and between the substrate (1) and the well region (9), the impurity concentration being chosen higher than that of the drain diffused region (7).
References Cited (Backward Citations)
No citation records indexed.
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