§
Luxuse
Patent Intelligence
Sign In
← Back to Patent Explorer
EP0193116A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Method of manufacturing a semiconductor device having a trench

Assignee: Toshiba Corp
•
Filing: 1986-02-20
•
Granted: —
•
Expires: 2006-02-20
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method of manufacturing a semiconductor device, comprising the steps of sequentially forming a buried region (32) and an epitaxial layer (33) on a major surface of a semiconductor substrate (31), forming a conductive layer (40') along an annular trench (38) extending to the buried region (32), filling the annular trench with an insulating material (41) and forming a functional element in said epitaxial layer (33) surrounded by said buried region (32) and said insulating material (41) within said annular trench. In this method, the step of forming the conductive layer (40') along the annular trench (38) is carried out by the steps of forming an annular trench (38) extending through said buried region (32), and depositing a conductive layer (40') on only a side wall surface of said annular trench (38).

Inventors

  • 👤 Shin-Ichi C/O Patent Division Taka
  • 👤 Jiro C/O Patent Division Ohshima
  • 👤 Masahiro C/O Patent Division Abe
  • 👤 Masaharu C/O Patent Division Aoyama

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-01 10:31
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/80; H10D10/821; H10W; H10W20/00; H10W20/01; H10W20/021; H10D10/01

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 133 words
A method of manufacturing a semiconductor device, comprising the steps of: forming a buried region in the major surface of a semiconductor substrate; forming 'an epitaxial layer on the one major surface of said semiconductor substrate which includes said buried region; forming a conductive layer along an annular trench extending to said buried region; filling said annular trench with an insulating material; and forming a functional element in said epitaxial layer surrounded by said buried region and said insulating material within said annular trench, which is characterized in that the step of forming a conouctive layer along an annular trench is carried out by the steps of: (a) forming an annular trench extending through said buried region; and (b) depositing a conductive layer on only a side wall surface of said annular trench.
Claim 2
Independent Claim 133 words
A method of manufacturing a semiconductor device, comprising the steps of: forming a buried region in the major surface of a semiconductor substrate; forming 'an epitaxial layer on the one major surface of said semiconductor substrate which includes said buried region; forming a conductive layer along an annular trench extending to said buried region; filling said annular trench with an insulating material; and forming a functional element in said epitaxial layer surrounded by said buried region and said insulating material within said annular trench, which is characterized in that the step of forming a conouctive layer along an annular trench is carried out by the steps of: (a) forming an annular trench extending through said buried region; and (b) depositing a conductive layer on only a side wall surface of said annular trench.
Claim 3
Dependent Claim 30 words
A method according to claim 1, characterized in that the step (a) comprises the step of forming an annular trench having a wall surface substantially perpendicular to said semiconductor substrate.
Claim 4
Dependent Claim 46 words
A method according to claim 1, characterized in that the step (b) comprises the step of depositing impurity-doped polysilicon on an inner surface of said annular trench and then etching the impurity-doped polysilicon by reactive ion etching to leave a remaining portion as a conductive layer.
Claim 5
Dependent Claim 17 words
A method according to claim 3, characterized in that impurity-doped polysilicon is deposited by chemical vapor deposition.
Claim 6
Dependent Claim 18 words
A method according to claim 3, characterized in that said impurity-doped polysilicon is deposited by physical vapor deposition.
Claim 7
Dependent Claim 18 words
A method according to claim 3, characterized in that said functional element formed is a bipolar semiconductor device.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag