Integrated circuit with a semiconductor capacitor and process for its production

Claim 2

A semiconductor integrated circuit comprising a) a capacitor device including a first conductive layer on a semiconductor substrate, an insulating layer on the first conductive layer and a second conductive layer of polysilicon on the insulating layer, b) an insulating layer covering said second conductive layer and formed with a plurality of openings each extending to the surface of the second conductive layer, and c) a metal layer formed on the insulating layer on said second conductive layer, the metal layer having portions contacting said second conductive layer respectively through said openings.

Claim 3

A semiconductor integrated circuit as set forth in claim 1, in which said openings in the insulating layer on said second conductive layer are distributed substantially uniformly over the insulating layer on said second conductive layer.

Claim 4

A semiconductor integrated circuit as set forth in claim 2, in which each of said openings in the insulating layer on said second conductive layer is generally square-shaped in cross section and measures from about 1 by 1 square micron to about 4 by 4 square microns.

Claim 5

.A semiconductor integrated circuit as set forth in claim 3, in which each of said openings in the insulating layer on said second conductive layer is provided for a generally square-shaped unit area measuring from about 10 by 10 square microns to about 100 by 100 square microns.

Claim 6

A process of fabricating a semiconductor integrated circuit structure including a capacitor device formed therein comprising, a) preparing a semiconductor substrate of a predetermined conductivity type, b) forming a relatively thick oxide layer on the substrate, c) forming a first conductive layer on said relatively thick oxide layer, d) forming a relatively thin oxide film on the first conductive layer, e) forming a second conductive layer of polysilicon on this relatively thin oxide film for thereby providing said capacitor device composed of said first conductive layer, said insulating layer on the first conductive layer and said second conductive layer of polysilicon, f) forming an outer insulating layer on the entire surface of the resultant structure, g) patterning and etching the outer insulating layer for forming therein contact holes including a plurality of contact holes extending to the surface of said second conductive layer, and h) forming a metal layer having a plurality of lug portions contacting said second conductive layer respectively through said contact holes extending to the surface of the second conductive layer.

Claim 7

A process of fabricating a semiconductor integrated circuit structure including a capacitor device formed therein comprising, a) preparing a semiconductor substrate of a predetermined conductivity type, b) forming a relatively thick oxide layer on the substrate, c) forming a first conductive layer on said relatively thick oxide layer, d) forming a relatively thin oxide film on the first conductive layer, e) forming a second conductive layer of polysilicon on this relatively thin oxide film for thereby providing said capacitor device composed of said first conductive layer, said insulating layer on the first conductive layer and said second conductive layer of polysilicon, f) forming an outer insulating layer on the entire surface of the resultant structure, g) patterning and etching the outer insulating layer for forming therein contact holes including a plurality of contact holes extending to the surface of said second conductive layer, and h) forming a metal layer having a plurality of lug portions contacting said second conductive layer respectively through said contact holes extending to the surface of the second conductive layer.

Claim 8

A process of fabricating a semiconductor integrated circuit structure as set forth in claim 5, further comprising the step of i) injecting a dopant of said predetermined conductivity type into said second conductive layer control the sheet resistance of the layer to a predetermined value.

Claim 9

A process of fabricating a semiconductor integrated circuit structure including a capacitor device and a MOS device formed therein comprising, a) preparing a semiconductor substrate of a first conductivity type, b) forming a channel stop region in the substrate adjacent an active region to form said MOS device, c) forming a relatively thick oxide... layer on the substrate, the oxide layer in part overlying said channel stop region, d) forming a relatively thin gate oxide film on the exposed surface portion of the substrate adjacent said relatively thick oxide layer, e) forming a first conductive layer on said relatively thick oxide layer and a gate region on said gate oxide film, f) forming a relatively thin oxide film on the first conductive layer, g) forming a second conductive layer of polysilicon on this relatively thin oxide film for thereby providing said capacitor device composed of said first conductive layer, said insulating layer on the first conductive layer and said second conductive layer of polysilicon, h) injecting a dopant of said first conductivity type into said second conductive layer control the sheet resistance of the layer to a predetermined value, i) injecting a dopant of a second conductivity type into said active region of said substrate outside said gate region for producing source and drain regions in the substrate for thereby providing said MOS transistor composed of said gate region and said source and drain regions, said second conductivity type being opposite to said first conductivity type j) forming an outer insulating layer on the entire surface of the resultant structure, k) patterning and etching the outer insulating layer for forming therein contact holes including a plurality of contact holes extending to the surface of said second conductive layer and contact holes extending to the surfaces of said source and drain regions, respectively, of said substrate, and 1) forming a metal layer having a plurality of lug portions contacting said second conductive layer respectively through said contact holes extending to the surface of the second conductive layer, and metal layers contacting said source and drain regions of said substrate respectively through said contact holes extending to the surfaces of said source and drain regions, respectively, of said substrate.

Claim 10

A process of fabricating a semiconductor integrated circuit structure including a capacitor device and a MOS device formed therein comprising, a) preparing a semiconductor substrate of a first conductivity type, b) forming a channel stop region in the substrate adjacent an active region to form said MOS device, c) forming a relatively thick oxide... layer on the substrate, the oxide layer in part overlying said channel stop region, d) forming a relatively thin gate oxide film on the exposed surface portion of the substrate adjacent said relatively thick oxide layer, e) forming a first conductive layer on said relatively thick oxide layer and a gate region on said gate oxide film, f) forming a relatively thin oxide film on the first conductive layer, g) forming a second conductive layer of polysilicon on this relatively thin oxide film for thereby providing said capacitor device composed of said first conductive layer, said insulating layer on the first conductive layer and said second conductive layer of polysilicon, h) injecting a dopant of said first conductivity type into said second conductive layer control the sheet resistance of the layer to a predetermined value, i) injecting a dopant of a second conductivity type into said active region of said substrate outside said gate region for producing source and drain regions in the substrate for thereby providing said MOS transistor composed of said gate region and said source and drain regions, said second conductivity type being opposite to said first conductivity type j) forming an outer insulating layer on the entire surface of the resultant structure, k) patterning and etching the outer insulating layer for forming therein contact holes including a plurality of contact holes extending to the surface of said second conductive layer and contact holes extending to the surfaces of said source and drain regions, respectively, of said substrate, and 1) forming a metal layer having a plurality of lug portions contacting said second conductive layer respectively through said contact holes extending to the surface of the second conductive layer, and metal layers contacting said source and drain regions of said substrate respectively through said contact holes extending to the surfaces of said source and drain regions, respectively, of said substrate.

Claim 11

A process of fabricating a semiconductor integrated circuit structure as set forth in claim 5, 6 or 7, in which said contact holes are formed in said outer insulating layer by an etching process including a wet etching step using an etchant of hydrofluoric acid.