EP0192366A2
Expired / Lapsed
EP
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Apparatus and method for improving system bus performance in a data processng system
Assignee: Digital Equipment Corp
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Filing: 1986-01-31
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Granted: —
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Expires: 2006-01-31
Abstract
Abstract In a data.processing system in which a plurality of data processing units, as well as the main memory unit, are coupled to a system bus, the utilization of the system bus is Increased to such an extent that each of a plurality of cache memory units coupled to the system bus can have a plurality of data processing units associated therewith. The system bus utilization is increased by dividing the system bus access operation into a plurality of sub-operations and by providing a defined cyclic sequence for the cache memory units to have access to the system bus.
Inventors
- 👤 Stephen Jay Shaffer
- 👤 Richard Alan Warren
- 👤 Thomas W. Eggers
- 👤 William D. Strecker
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 22:24
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/084; G06F12/0844; G06F12/0846; G06F12/10; G06F12/1027; G06F12/1045; G06F13/362; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
76 words
A data processing system comprising: a system bus for transfer of logic signals; a main memory unit for storing groups of logic signals coupled to said system bus; a first plurality of data processing units for processing selected groups of logic signals; and a second plurality of cache memory units, said cache memory units being coupled to said system bus and wherein a plurality of data processing units can be coupled to each cache memory unit.
Claim 2
Dependent Claim
76 words
A data processing system comprising: a system bus for transfer of logic signals; a main memory unit for storing groups of logic signals coupled to said system bus; a first plurality of data processing units for processing selected groups of logic signals; and a second plurality of cache memory units, said cache memory units being coupled to said system bus and wherein a plurality of data processing units can be coupled to each cache memory unit.
Claim 3
Dependent Claim
29 words
A data processing system as claimed in Claim 1 wherein an access operation of said system bus by a cache memory unit is divided into a plurality of sub-operations.
Claim 4
Dependent Claim
43 words
A data processing system as claimed in Claim 2 wherein said access to said system bus occurs during a series of predetermined time intervals as controlled by a system bus arbiter, said sub-operations by said cache unit not occurring during successive time intervals.
Claim 5
Dependent Claim
23 words
A data processing system as claimed in Claim 1 wherein said cache memory unit is divided into a plurality of cache memory sub-units.
Claim 6
Dependent Claim
39 words
A data pocessing system as claimed in Claim 1 wherein said main memory unit further includes apparatus for combining an input data signal group with a data signal group stored in said main memory unit at a defined address.
Claim 7
Dependent Claim
35 words
A data processing system as claimed in Claim 1 wherein said system bus is divided into a control signal bus, an address signal bus, a read data signal bus and a write data signal bus.
Claim 8
Dependent Claim
28 words
A data processing system as claimed in Claim 6 wherein a plurality of said cache memory units can interact with said system bus during a selected time interval.
Claim 9
Dependent Claim
29 words
A data processing system as claimed in Claim 3 wherein an access sub-operation of a first cache memory unit occurs between access sub-operations of a second cache memory unit.
Claim 10
Dependent Claim
78 words
A data processing system including a system bus for transfer of logic signals; a main memory for storing groups of logic signals, coupled to said system bus; a first plurality of data processing units for processing selected groups of logic signals; and a second plurality of cache memory units coupled to said system bus and including means for multiplexing the transfer of logic signals on said data bus to increase the maximum effective data rate on said bus.
Claim 11
Dependent Claim
78 words
A data processing system including a system bus for transfer of logic signals; a main memory for storing groups of logic signals, coupled to said system bus; a first plurality of data processing units for processing selected groups of logic signals; and a second plurality of cache memory units coupled to said system bus and including means for multiplexing the transfer of logic signals on said data bus to increase the maximum effective data rate on said bus.
Claim 12
Independent Claim
94 words
A method for transferring signal groups on a system bus in a data processing system from a memory unit and from a plurality of cache memory units, comprising the steps of: arranging access to said system bus into a sequence of time intervals; dividing a system bus access operation into a plurality of system bus access sub-operations; and executing said bus access operations by a first cache memory unit during nonconsecutive time intervals, wherein a second cache memory unit can perform a system bus access sub-operation between sub-operation of said first cache memory unit.
Claim 13
Independent Claim
94 words
A method for transferring signal groups on a system bus in a data processing system from a memory unit and from a plurality of cache memory units, comprising the steps of: arranging access to said system bus into a sequence of time intervals; dividing a system bus access operation into a plurality of system bus access sub-operations; and executing said bus access operations by a first cache memory unit during nonconsecutive time intervals, wherein a second cache memory unit can perform a system bus access sub-operation between sub-operation of said first cache memory unit.
Claim 14
Dependent Claim
68 words
ll. A method as claimed in Claim 10 further ccnprising the steps of: dedicating a portion of said system bus to data signal groups from said cache memory unit; dedicating a portion of said system bus to data signal groups from said memory unit; and dedicating a portion of said system bus to address signal groups, said address signal groups definirg a one of said data signal groups.
Claim 15
Dependent Claim
64 words
The method as claimed in Claim 11 further comprising the step of: dividing a system bus access operation into sub-operation steps of: applying an address signal group to said system bus; applying a data signal group from a cache memory unit with access to said system bus to said system bus; and applying a data signal group from said memory unit to said system.
Claim 16
Dependent Claim
27 words
The method as claimed in Claim 12 further including the step of combining said cache memory unit data signal group with said memory unit data signal group.
Claim 17
Dependent Claim
28 words
The method as claimed in Claim 12 further including the step of coupling a plurality of data processing units to at least one of said cache memory units.
Claim 18
Dependent Claim
43 words
The method as claimed in Claim 14 further including the step of dividing each cache memory unit into a plurality of cache memory sub-units, each of said cache memory sub-units being independently accessible by data processing units coupled to said cache memory unit.
Claim 19
Dependent Claim
166 words
A data processing system comprising: bus means for distributing groups of logic signals through said data processing system; memory means coupled to said bus means for storing a plurality of data signal groups each of said data signal groups idendified by an address signal group; a plurality of cache memory means coupled to said bus means for storing a subset of said memory means data signal groups; and data processing means coupled to each of said cache memory means, wherein said data processing means applies a selected address to said coupled cache memory means, said cache memory means applying said selected address signal group to said identified bus means when said data signal group by said selected address signal is not stored in said coupled cache memory means, said selected address signal group applied to said bus means during a one of a sequence of time intervals, said cache memory means receiving said identified data signal group from said bus means during a non-consecutive time interval.
Claim 20
Dependent Claim
166 words
A data processing system comprising: bus means for distributing groups of logic signals through said data processing system; memory means coupled to said bus means for storing a plurality of data signal groups each of said data signal groups idendified by an address signal group; a plurality of cache memory means coupled to said bus means for storing a subset of said memory means data signal groups; and data processing means coupled to each of said cache memory means, wherein said data processing means applies a selected address to said coupled cache memory means, said cache memory means applying said selected address signal group to said identified bus means when said data signal group by said selected address signal is not stored in said coupled cache memory means, said selected address signal group applied to said bus means during a one of a sequence of time intervals, said cache memory means receiving said identified data signal group from said bus means during a non-consecutive time interval.
Claim 21
Dependent Claim
44 words
A data processing system as claimed in Claim 16 wherein a second cache memory means can apply logic signals to said bus means or receiving logic signals from said bus means during a time interval between said one time interval and said non-consecutive interval.
Claim 22
Dependent Claim
47 words
A data processing system as claimed in Claim 17 wherein said bus means includes an address sub-bus means for distributing address signals receiving and address signal groups from said cache memory means and includes a first sub-bus for distributing data signal groups received from said memory means.
Claim 23
Dependent Claim
52 words
A data processing system as claimed in Claim 18 wherein said cache memory means can apply a preestablished data signal group to a second sub-bus means for distribution during a second time interval following and non-consecutive with said one time interval and for distribution preceding and non-consecutive with said non-consecutive time interval.
Claim 24
Dependent Claim
27 words
A data processing system as claimed in Claim 19 wherein at least one of said cache memory means is coupled to a plurality of data processing means.
Claim 25
Dependent Claim
33 words
A data processing system as claimed in Claim 20 wherein each of said cache memory means includes a plurality of sub-cache memory means for being independently accessed by said coupled data processing means.
Claim 26
Dependent Claim
40 words
A data processing system as claimed in Claim 19 wherein said memory means includes means for combining data signals from said second sub-bus means and said memory means and applying a modified data signal group to said first sub-bus means.
Claim 27
Dependent Claim
144 words
A data processing system comprising: a system bus for distributing logic signal groups; a memory means for storing a multiplicity of data signal groups, each of said data signal groups associated with an address signal group; a plurality of cache memory means for storing selected data signal groups; said cache memory means being coupled to said system bus; and data processing means coupled to each of said cache memory means said data processing means manipulating a data signal group retrieved from said coupled cache memory means when an applied address signal group identifying a selected data signal group is applied to said cache memory means; said plurality of cache memory means including multiplexing means for multiplexing a plurality of sub-operations, said plurality of sub-operations retrieving said identified data signal group when said identified data signal group is not in said coupled cache memory means.
Claim 28
Dependent Claim
144 words
A data processing system comprising: a system bus for distributing logic signal groups; a memory means for storing a multiplicity of data signal groups, each of said data signal groups associated with an address signal group; a plurality of cache memory means for storing selected data signal groups; said cache memory means being coupled to said system bus; and data processing means coupled to each of said cache memory means said data processing means manipulating a data signal group retrieved from said coupled cache memory means when an applied address signal group identifying a selected data signal group is applied to said cache memory means; said plurality of cache memory means including multiplexing means for multiplexing a plurality of sub-operations, said plurality of sub-operations retrieving said identified data signal group when said identified data signal group is not in said coupled cache memory means.
Claim 29
Dependent Claim
31 words
A data processing system as claimed in Claim 23 wherein said system bus includes an address signal bus, a first data signal group bus and a second data signal group bus.
Claim 30
Dependent Claim
33 words
A data processing system as claimed in Claim 24 wherein said memory means includes means for combining data signal groups from said first sub-bus and data signal groups stored in said memory means.
Claim 31
Dependent Claim
27 words
A data processing system as claimed in Claim 25 wherein at least one of said cache memory means is coupled to a plurality of data processing means.
Claim 32
Dependent Claim
30 words
A data processing system as claimed in Claim 26 wherein said cache memory means includes a plurality of sub-cache memory means for independent access by said coupled data processing means.
References Cited (Backward Citations)
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