EP0192121A2
Expired / Lapsed
EP
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Test circuit for a cross-coupled transistor storage cell
Assignee: International Business Machines Corp
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Filing: 1986-02-05
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Granted: —
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Expires: 2006-02-05
Abstract
Abstract A test circuit is provided wherein data is stored in circuits or cells of an array or matrix with the use of conventional or normal operating voltages. Voltages at internal nodes of the circuits or cells are altered to magnitudes beyond the normal operating ranges, which includes significantly decreasing the offset voltage, for a short period of time and then the stored data is read out at normal voltages and currents and compared with the data written into the circuits or cells.
Inventors
- 👤 Roy Childs Flaker
- 👤 Russell James Houghton
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 14:48
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/50; G11C29/50016; G06; G06F; G06F2201/00; G06F2201/81
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
68 words
A test circuit for a cross-coupled transistor cell (10) having first and second storage nodes (N1, N2) with a given offset voltage therebetween storing a given digit of binary data characterized by means ( 44 , 30, D5) for decreasing said offset voltage, means (V c , D6, D7) for increasing the voltage applied to one of said nodes, and means (22) for reading data from said cell.
Claim 2
Dependent Claim
68 words
A test circuit for a cross-coupled transistor cell (10) having first and second storage nodes (N1, N2) with a given offset voltage therebetween storing a given digit of binary data characterized by means ( 44 , 30, D5) for decreasing said offset voltage, means (V c , D6, D7) for increasing the voltage applied to one of said nodes, and means (22) for reading data from said cell.
Claim 3
Dependent Claim
32 words
A test circuit according to claim 1, characterized in that said means for decreasing said offset voltage includes means (44, 3 0 , D5) for decreasing the current flow through said cell.
Claim 4
Dependent Claim
22 words
A test circuit according to claim 2, characterized in that said offset voltage decreasing means includes a standby current reference circuit (30).
Claim 5
Dependent Claim
28 words
A test circuit according to claim 1, characterized in that said voltage increasing means includes an isolation region having a voltage varying terminal (V c ) connected thereto.
Claim 6
Dependent Claim
44 words
A test circuit according to claim 1, characterized in that said offset voltage decreasing means (44, 30, D5) decreases said voltage during a first period of time and said data reading means (22) reads data from said cell after said first period of time.
Claim 7
Dependent Claim
65 words
A test circuit according to claim 1, characterized by further including a pair of bit lines (B0, 81), means (46) for applying an operating voltage to said bit lines during a first period of time and means (46, D3, D4) for applying a voltage to said bit line during a second period of time having a magnitude significantly larger than that of said operating voltage.
Claim 8
Dependent Claim
34 words
A test circuit according to claim 2, characterized in that said current decreasing means further includes means for altering the voltage at the voltage supply source (Vc) of said standby current reference circuit (30).
Claim 9
Dependent Claim
31 words
A test circuit according to claim 7, characterized in that said voltage altering means increases the voltage at the voltage supply source (V c ) of said standby current reference circuit
References Cited (Backward Citations)
No citation records indexed.
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