EP0190935A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method of manufacturing semiconductor devices using a bonding process
Assignee: Toshiba Corp
•
Filing: 1986-02-06
•
Granted: —
•
Expires: 2006-02-06
Abstract
Abstract Disclosed is a method of manufacturing a semiconductor device, comprising the step of forming a semiconductor wafer having a first impurity-doped layer and a second impurity-doped layer having a higher impurity concentration than that of the first impurity-doped layer, comprising the steps of bringing a first semiconductor substrate (11), having a third impurity-doped layer (12) which has a higher impurity concentration than that of the first impurity-doped layer and the same conductivity type as that of the second impurity-doped layer, and whose surface is mirror-polished, into contact with a second semiconductor substrate (13) having a fourth impurity doped layer, which has a higher impurity concentration than that of the first impurity-doped layer and the same conductiviey type as that of the second impurity-doped layer, and whose surface is mirror-polished, so that the mirror-polished surfaces thereof are in contact with each other, and in a clean atmosphere so that virtually no foreign substances are present therebetween, and annealing the first and second semiconductor substrates (11,13) whose mirror-polished surfaces are in contact with each other at a temperature of not less than 200°C so as to bond them together, thereby forming the second impurity-doped layer consisting of the third and fourth impurity-doped layers.
Inventors
- 👤 Akio C/O Patent Division Nakagawa
- 👤 Hiromichi C/O Patent Division Ohashi
- 👤 Tsuneo C/O Patent Division Ogura
- 👤 Masaru C/O Patent Division Shimbo
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 05:22
CPC Classifications
H; H10; H10P; H10P70/00; H10P70/10; H10P70/15; H10P10/00; H10P10/12; H10P10/128
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
198 words
A method of manufacturing a semiconductor device, comprising the step of forming a semiconductor wafer having a first impurity-doped layer and a second impurity-doped layer having a higher impurity concentration than that of said first impurity-doped layer, comprising the steps of: bringing a first semiconductor substrate (11), having a third impurity-doped layer (12) which has a higher impurity concentration than that of said first impurity-doped layer and the same conductivity type as that of said second impurity-doped layer, and whose surface is mirror-polished, into contact with a second semiconductor substrate (13) having a fourth impurity-doped layer, which has a higher impurity concentration than that of said first impurity-doped layer and the same conductivity type as that of said second impurity-doped layer, and whose surface is mirror-polished, so that the mirror-polished surfaces thereof are in contact with each other, and in a clean atmosphere so that virtually no foreign substances are present therebetween; and annealing said first and second semiconductor-substrates (11, 13) whose mirror-polished surfaces are in contact with each other at a temperature of not less than 200°C so as to bond them together, thereby forming said second impurity-doped layer consisting of said third and fourth impurity-doped layers.
Claim 2
Independent Claim
198 words
A method of manufacturing a semiconductor device, comprising the step of forming a semiconductor wafer having a first impurity-doped layer and a second impurity-doped layer having a higher impurity concentration than that of said first impurity-doped layer, comprising the steps of: bringing a first semiconductor substrate (11), having a third impurity-doped layer (12) which has a higher impurity concentration than that of said first impurity-doped layer and the same conductivity type as that of said second impurity-doped layer, and whose surface is mirror-polished, into contact with a second semiconductor substrate (13) having a fourth impurity-doped layer, which has a higher impurity concentration than that of said first impurity-doped layer and the same conductivity type as that of said second impurity-doped layer, and whose surface is mirror-polished, so that the mirror-polished surfaces thereof are in contact with each other, and in a clean atmosphere so that virtually no foreign substances are present therebetween; and annealing said first and second semiconductor-substrates (11, 13) whose mirror-polished surfaces are in contact with each other at a temperature of not less than 200°C so as to bond them together, thereby forming said second impurity-doped layer consisting of said third and fourth impurity-doped layers.
Claim 3
Dependent Claim
48 words
A method according to claim 1, characterized in that said first and second impurity-doped layers are of the same conductivity type, said first semiconductor substrate (11) consists of said first and third impurity-doped layers, and said second semiconductor substrate (13) is entirely formed by said fourth impurity-doped layer.
Claim 4
Dependent Claim
86 words
A method according to claim 1, characterized in that said first and second impurity-doped layers are of different conductivity types; said first semiconductor substrate (21) consists of said first impurity-doped layer, a fifth impurity-doped layer (22) formed thereon which has a higher impurity concentration than that of said first impurity-doped layer and is of the same conductivity type as that of said first impurity-doped layer, and said third impurity-doped layer (23) formed thereon; and said second-semiconductor layer (24) is entirely formed by said fourth impurity-doped layer.
Claim 5
Dependent Claim
102 words
A method according to claim 1, characterized in that said first and second impurity-doped layers are of the same conductivity type; said first semiconductor substrate (31) consists of said first impurity-doped layer, sixth and seventh impurity-doped layers (32, 33), which are formed at two sides thereof, and have a higher impurity concentration than that of said first impurity-doped layer and the conductivity type opposite thereto, and said third impurity-doped layer (34), formed on that at a bonding surface side of said sixth and seventh impurity-doped layers (32, 33); and said second semiconductor substrate (35) is entirely formed by said fourth impurity-doped layer.
Claim 6
Dependent Claim
24 words
A method according to claim 1, characterized in that said semiconductor device is a diode, and said second impurity-doped layer serves as a cathode.
Claim 7
Dependent Claim
33 words
A method according to claim 1, characterized in that said semiconductor device is a conductivity modulation type metal oxide semiconductor device or a thyristor, and said second impurity-doped layer serves as an emitter.
Claim 8
Dependent Claim
22 words
A method according to claim 1, characterized in that a roughness of the mirror-polished surface is not 0 more than 500 A.
Claim 9
Dependent Claim
20 words
A method according to claim 1, characterized in that an annealing temperature falls within the range of 1,000 to 1,200°C.
Claim 10
Dependent Claim
40 words
A method according to claim 1, characterized in that an oxide film is formed on said third impurity-doped layer, and said step of forming a semiconductor wafer further comprises removing the oxide film from said third impurity-doped layer before bonding.
Claim 11
Dependent Claim
48 words
A method according to claim 9, characterized in that said first and second impurity-doped layers are of the same conductivity type, said first semiconductor substrate (11) consists of said first and third impurity-doped layers, and said second semiconductor substrate (13) is entirely formed by said fourth impurity-doped layer.
Claim 12
Dependent Claim
88 words
A method according to claim 9, characterized in that said first and second impurity-doped layers are of different conductivity types; said first semiconductor substrate (21) consists of said first impurity-doped layer (22), a fifth impurity-doped layer formed thereon which has a higher impurity concentration than that of ; said first impurity-doped layer and is of the same conductivity type as that of said first impurity-doped layer, and said third impurity-doped layer (23) formed thereon; and said second semiconductor layer (24) is entirely formed by said fourth impurity-doped layer.
Claim 13
Dependent Claim
101 words
A method according to claim 9, characterized in that said first and second impurity-doped layers are of the same conductivity type; said first semiconductor substrate (31) consists of said first impurity-doped ; layer, sixth and seventh impurity-doped layers (32, 33), which are formed at two sides thereof, and have a higher impurity concentration than that of said first impurity-doped layer and the conductivity type opposite thereto, and said third impurity-doped layer (34), formed on that at a bonding surface side of said sixth and seventh impurity-doped layers; and said second semiconductor substrate (35) is entirely formed by said fourth impurity-doped layer.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.