Patent US1888263A successfully refreshed from Google Patents.
EP0190934A2
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EP
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Method of manufacturing a thyristor
Assignee: Toshiba Corp
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Filing: 1986-02-06
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Granted: —
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Expires: 2006-02-06
Abstract
Abstract Disclosed is a method of manufacturing a thyristor having a base layer comprising impurity layers which are bonded to each other, comprising the steps of bringing a first semiconductor substrate (11) having a first impurity layer (12) whose surface is mirror-polished into contact with a second semiconductor substrate (13) whose surface is mirror-polished and which is of the same conductivity type as the first impurity layer (12), so that the mirror-polished surfaces are in contact with each other, and in a pure atmosphere so that virtually no foreign substances are present therebetween, and annealing the first and second semiconductor substrates whose mirror-polished surfaces are in contact with each other at a temperature of not less than 200°C so as to bond the mirror-polished surfaces together, thereby forming the base layer consisting of the impurity layer and the second semiconductor substrate.
Inventors
- 👤 Tsuneo C/O Patent Division Ogura
- 👤 Hiromichi C/O Patent Division Ohashi
- 👤 Akio C/O Patent Division Nakagawa
- 👤 Masaru C/O Patent Division Shimbo
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 21:26
CPC Classifications
H; H10; H10P; H10P70/00; H10P70/10; H10P70/15; H10D; H10D18/00; H10D18/60; H10D62/00; H10D62/10; H10D62/17; H10D62/192; H10D62/206; H10D62/60; H10P10/00; H10P10/12; H10P10/128
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
143 words
A method of manufacturing a thyristor having a base layer comprising first and second impurity layers which are bonded to each other, comprising the steps of: bringing, in an atmosphere virtually free of particulate matter, a first semiconductor substrate (11) having a first impurity layer (12) whose surface is mirror polished into contact with a second semiconductor substrate (13) having a second impurity layer whose surface is mirror polished and which is of the same conductivity type as said first impurity layer, such that no foreign substances interfere with their contact; and annealing said first and second semiconductor substrates (11, 13), whose said mirror polished surfaces are in contact with each other, at a temperature of not less than 200°C so as to bond the mirror polished surfaces together and thereby form a base layer consisting of said first and second impurity layers.
Claim 2
Independent Claim
143 words
A method of manufacturing a thyristor having a base layer comprising first and second impurity layers which are bonded to each other, comprising the steps of: bringing, in an atmosphere virtually free of particulate matter, a first semiconductor substrate (11) having a first impurity layer (12) whose surface is mirror polished into contact with a second semiconductor substrate (13) having a second impurity layer whose surface is mirror polished and which is of the same conductivity type as said first impurity layer, such that no foreign substances interfere with their contact; and annealing said first and second semiconductor substrates (11, 13), whose said mirror polished surfaces are in contact with each other, at a temperature of not less than 200°C so as to bond the mirror polished surfaces together and thereby form a base layer consisting of said first and second impurity layers.
Claim 3
Dependent Claim
17 words
A method according to claim 1, characterized in that said base layer is a p-type base layer.
Claim 4
Dependent Claim
61 words
A method according to claim 2, characterized in that said first semiconductor substrate is an n -type silicon substrate (11) which serves as a high resistance n-type base layer and said first impurity layer is a first p-type layer (12) formed on a junction surface of said n -type silicon substrate (11) and constituting a portion of said p-type base layer.
Claim 5
Dependent Claim
33 words
A method according to claim 3, characterized in that said second semiconductor substrate is a p-type silicon substrate (13) with a uniform impurity concentration constituting the remaining portion of said p-type base layer.
Claim 6
Dependent Claim
53 words
A method according to claim 3, characterized in that said second semiconductor substrate is a high resistance p-type silicon substrate (23) and said second impurity layer is a second p-type layer (24) formed on a junction surface of said p-type silicon substrate (23) and constituting the remaining portion of said p-type base layer.
Claim 7
Dependent Claim
50 words
A method according to claim 3, characterized in that said second semiconductor substrate is a second n-type silicon substrate and said second impurity layer is a second p-type layer formed on a junction surface of said second n-type silicon substrate and constituting the remaining portion of said p-type base layer.
Claim 8
Dependent Claim
95 words
A method according to claim 4, characterized in that one or more first p-type regions (33) having a higher impurity concentration than that of said first p-type layer (32) are selectively formed on the junction surface of said first p-type layer (32), second p-type regions (35) having a higher impurity concentration than that of said p-type silicon substrate (34) are formed at positions of said p-type silicon substrate (34) corre-' sponding to said first p-type regions (33) formed on the junction surface, and said first and second p-type regions (33, 35) constitute a gate region.
Claim 9
Dependent Claim
28 words
A method according to claim 5, characterized in that the impurity concentration of said first p-type layer (22) is lower than that of said second p-type layer (24).
Claim 10
Dependent Claim
31 words
A method according to claim 5, characterized in that the impurity concentration of said first p - type layer (22) is substantially equal to that of said second p-type layer (24).
Claim 11
Dependent Claim
28 words
A method according to claim 5, characterized in that the impurity concentration of said first p-type layer (22) is higher than that of said second p-type layer (24).
Claim 12
Dependent Claim
20 words
11, A method according to claim 1, characterized in that said base layer is a low resistance n-type base layer,
Claim 13
Dependent Claim
113 words
A method according to claim 11, characterized in that said first semiconductor substrate is a first n -type silicon substrate (51) forming a high resistance n-type base layer, said first impurity layer is a first n-type layer (52) formed on a junction surface of said first n - -type silicon substrate (51) and constituting a portion of said low resistance n-type base layer, said second semiconductor substrate is a second n - -type silicon substrate (53), and said second impurity layer is a second n-type layer (54) formed on a junction surface of said second n - -type silicon substrate (53) and constituting the remaining portion of said low resistance n-type base layer.
Claim 14
Dependent Claim
30 words
A method according to claim 1, further comprising the step of polishing that surface of said second semiconductor substrate opposite a junction surface thereof so as to decrease its thickness.
Claim 15
Dependent Claim
19 words
A method according to claim 1, characterized in that the adopted optical polishing method is a mirror polishing method.
Claim 16
Dependent Claim
23 words
A method according to claim 1, characterized in that the roughness of the mirror polished surface is not 0 more than 500 A.
Claim 17
Dependent Claim
37 words
A method according to claim 1, characterized in that the mirror polished surface is washed with at least one washing solution selected from the group consisting of water, a surfactant, an organic solvent, and an acid solution.
Claim 18
Dependent Claim
27 words
A method according to claim 1, characterized in that the pure atmosphere contains foreign substances at . a level of not more than 20 particles/m 3 ..
Claim 19
Dependent Claim
20 words
A method according to claim 1, characterized in that the annealing temperature falls within the range of 600 to 1200°C.
References Cited (Backward Citations)
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