Integrated MOS transistor and method of manufacturing it

Abstract

Abstract This invention is aimed at providing a semiconductor device of high degree of circuit integration and high reliability, and a method of manufacturing such devices in high yield. This invention provides a semiconductor device provided with: a gate electrode (49) provided on a semiconductor substrate (41) of a first conductivity type and with an insulating film (47, 48) arrranged above and below it; and a pair of first impurity regions (50 1 , 51,) of a second conductivity type provided mutually separated and self-aligned with said gate electrode (49) in said substrate (41); characterized in that a wall (54) consisting of insulator provided on at least one side face of said gate electrode (49) and said upper and lower insulating films (47. 48); a second highly doped impurity region (50 2 . 51 2 ) of second conductivity type provided in a self-aligned manner with respect to said wall (54) in said substrate, an electrode layer (59) connected to said second impurtiy region (50 2 , 51 7 ) and whereof at least a portion extends over said upper insulating film (47) of siad gate electrode (49); and a wiring layer selectively connected with said electrode layer. By means of this invention, as mentioned above, semiconductor devices of high degree of integration and high reliability can be manufactured in high yield.

Inventors

• 👤 Mitsugi C/O Patent Division Ogura
• 👤 Shoji C/O Patent Division Arizumi
• 👤 Fumio C/O Patent Division Horiguchi
• 👤 Fujio C/O Patent Division Masuoka

Bibliographic Details