EP0190813A2
Expired / Lapsed
EP
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Processing cell for fault tolerant arrays
Assignee: Qinetiq Ltd
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Filing: 1986-01-03
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Granted: —
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Expires: 2006-01-03
Abstract
Abstract A processing cell (10) is provided for use in constructing fault tolerant arrays. It contains a processor (12) arranged to indicate a faulty or fault-free operational state. The cell (10) is arranged to receive input from any one of three western neighbours, and to provide output to any one of three eastern neighbours. It both generates and receives connection request and availability signals. Internal logic ensures its becoming connected as part of an operational (not necessarily straight) row of cells (64) in an array (62) if and only if the processor (12) is fault-free and it receives at least one pair of true request and availability signals from respective eastern and western neighbours. The internal cell logic (16 to 52) implements a priority scheme in which connection to a more northern neighbour to east or west is preferred to connection to one more southern. This avoids any mid-array connection hiatus. Further embodiments (250,300,320) of the invention provide for reconfigurable columns of cells in addition to the foregoing row reconfiguration.
Inventors
- 👤 Richard Anthony Evans
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 11:41
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/006; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F15/8023; G06F11/00; G06F11/22; G06F11/26; G06F11/267
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
274 words
A processing cell (10) for use in constructing fault tolerant arrays (62), the cell (10) including a processor (12) for performing electronic operations on input signals and arranged to indicate its operational state, ie faulty or fault-free; characterised in that the cell (10) also includes: (a) at least one set of cell interconnection lines for connection to other cells in an array, the lines comprising a respective subset of first, second and third lines for each of the following: (i) processor input signals (IPW, IPNW, IPSW), (ii) processor output signals (OPE, OPNE, OPSE), (iii) input availability signals (AVAILE, AVAILNE, AVAILSE), (iv) input request signals (REQW, REQNW, REQSW), (v) output availability signals (AVAILW, AVAILNW, AVAILSW),and (vi) output request signals (REQE, REQNE, REQSE); wherein each processor input signal line (eg IPW) is associated with a respective input request signal line (eg REQW) and a respective output availability signal line (eg AVAILW), and each processor output signal line (eg OPE) is associated with a respective output request signal line (eg REQE) and a respective input availability signal line (eg AVAILE); (b) request signal generating means (20, 34 and 42 to 50) arranged to provide output request signals reflecting both processor operational state and input request and availability signals; (c) availability signal generating means (24, 28, 38) arranged to provide output availability signals reflecting both processor operational state and input request and availability signals; and (d) cell implementing means (16,18,22,26,30,32) arranged either to route signals to the processor (12) or to isolate it from such signals according to whether or not the cell (10) receives appropriate input request and input availability signals and the processor (12) is fault-free.
Claim 2
Dependent Claim
274 words
A processing cell (10) for use in constructing fault tolerant arrays (62), the cell (10) including a processor (12) for performing electronic operations on input signals and arranged to indicate its operational state, ie faulty or fault-free; characterised in that the cell (10) also includes: (a) at least one set of cell interconnection lines for connection to other cells in an array, the lines comprising a respective subset of first, second and third lines for each of the following: (i) processor input signals (IPW, IPNW, IPSW), (ii) processor output signals (OPE, OPNE, OPSE), (iii) input availability signals (AVAILE, AVAILNE, AVAILSE), (iv) input request signals (REQW, REQNW, REQSW), (v) output availability signals (AVAILW, AVAILNW, AVAILSW),and (vi) output request signals (REQE, REQNE, REQSE); wherein each processor input signal line (eg IPW) is associated with a respective input request signal line (eg REQW) and a respective output availability signal line (eg AVAILW), and each processor output signal line (eg OPE) is associated with a respective output request signal line (eg REQE) and a respective input availability signal line (eg AVAILE); (b) request signal generating means (20, 34 and 42 to 50) arranged to provide output request signals reflecting both processor operational state and input request and availability signals; (c) availability signal generating means (24, 28, 38) arranged to provide output availability signals reflecting both processor operational state and input request and availability signals; and (d) cell implementing means (16,18,22,26,30,32) arranged either to route signals to the processor (12) or to isolate it from such signals according to whether or not the cell (10) receives appropriate input request and input availability signals and the processor (12) is fault-free.
Claim 3
Dependent Claim
92 words
A processing cell (10) according to Claim 1 characterised in that the cell implementing means (16,18,22,26,30,32),request signal generating means (20,34 and 42 to 50) and availability signal generating means (24,28,38) are arranged in combination to operate a priority scheme in which use of each of the second processor input and output lines (IPW or OPE) is preferred to use of the respective third (IPSW or OPSE), and use of each of the first processor input and output lines (IPNW or OPNE) is preferred to use of the respective second (IPW or OPE).
Claim 4
Dependent Claim
56 words
A processing cell (10) according to Claim 1 or 2 characterised in that it includes a further input line (IPN) and a further output line (OPS), these lines being arranged either to route additional signals to and from the processor (12) or to bypass it in accordance with whether or not the processor (12) is fault-free.
Claim 5
Dependent Claim
25 words
A processing cell (64) according to Claim 2 or 3 characterised in that it is incorporated within a processing array.(62) of cells (64) equivalent thereto.
Claim 6
Dependent Claim
53 words
A processing cell (10) according to Claim 4 characterised in that it is incorporated in an array of cells (10) equivalent thereto accompanied by an input cell array (100) and an output cell array (200) arranged respectively to provide input to and output from operational rows of the array of cells (10) only.
Claim 7
Dependent Claim
83 words
A processing cell (250) according to Claim 1 for use in constructing two-dimensionally reconfigurable fault-tolerant cell arrays, characterised in that the cell (300 or 320) includes: (a) two sets of cell interconnection lines (eg IPW (Rows and OPS (Cols)),each set being as claimed in Claim 1, one set being arranged for row interconnection and the other for column interconnection, and (b) means (252 EW to 256 SW) for bypassing the processor in response to accurrence of a double site situation as herein defined.
Claim 8
Dependent Claim
38 words
A processing cell (300 or 320) according to Claim 6 characterised in that it includes means (302 to 312 or 332, 334) for bypassing the processor in response to occurrence of an improper crossover situation as herein defined.
References Cited (Backward Citations)
No citation records indexed.
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