EP0190490A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Thin-film electrical connections for integrated circuits
Assignee: AMI Semiconductor Inc
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Filing: 1985-11-21
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Granted: —
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Expires: 2005-11-21
Abstract
Abstract A method for fabricating thin-film multilayer interconnect signal planes for connecting semiconductor integrated circuits is described. In this method, a first pattern of thin-film metallic interconnect lines is formed on a surface of a substrate. Then a first dielectric layer is formed over the entire surface of the substrate covering the pattern of thin-film metallic interconnect lines. A portion of the dielectric layer is then removed to expose the thin-film metallic interconnect lines so that a series of trenches is formed above each interconnect line. The interconnect lines are then electroplated to form a series of thicker metal interconnect lines such that the thicker metal interconnect lines and the dielectric layer form a substantially planer surface. This process can then be repeated in its entirely to form a plurality of interconnect signal planes. In the preferred embodiment, metallic vias are provided between each layer of metallic interconnect lines for electrical connection purposes.
Inventors
- 👤 Peter L. Young
- 👤 Jay Cech
- 👤 Kin Li
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 21:09
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/69; H10W70/698; H05; H05K; H05K3/00; H05K3/10; H05K3/107; H05K3/46; H05K3/4644; H05K3/465; H10W70/01; H10W70/05; H10W70/611; H05K1/00; H05K1/02; H05K1/0286; H05K1/0287; H05K1/0289; H05K2201/00; H05K2201/01; H05K2201/0137; H05K2201/0154; H05K2201/03; H05K2201/0332; H05K2201/0364; H05K2201/0376; H05K2203/00; H05K2203/07; H05K2203/0703; H05K2203/0723; H05K2203/0733; H05K3/0011; H05K3/0017; H05K3/0023; H05K3/108; H05K3/22; H05K3/24; H05K3/241; H05K3/242; H05K3/244; H05K3/38; H05K3/388; H10W72/00; H10W72/851; H10W72/874; H10W72/884; H10W90/00; H10W90/701; H10W90/731; H10W90/734; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
146 words
A method of fabricating thin-film interconnect signal planes for connecting semiconductor integrated circuits comprising the steps of: forming a first pattern of thin-film metallic interconnect lines on a first surface of a substrate; forming a first dielectric layer on the entire area of said first surface of said substrate covering said first pattern of thin-film metallic interconnect lines; removing a portion of said first dielectric layer from said substrate in areas which cover said first thin-film metallic Interconnect lines to form a first series of trenches above each interconnect line; and electroplating said first pattern of thin-film metallic interconnect lines to form a first series of thicker metal interconnect lines on top of said first pattern of thin-film metallic interconnect lines in said first series of trenches, said first series of thicker metal interconnect lines and said first dielectric layer forming a first substantially planer surface.
Claim 2
Independent Claim
146 words
A method of fabricating thin-film interconnect signal planes for connecting semiconductor integrated circuits comprising the steps of: forming a first pattern of thin-film metallic interconnect lines on a first surface of a substrate; forming a first dielectric layer on the entire area of said first surface of said substrate covering said first pattern of thin-film metallic interconnect lines; removing a portion of said first dielectric layer from said substrate in areas which cover said first thin-film metallic Interconnect lines to form a first series of trenches above each interconnect line; and electroplating said first pattern of thin-film metallic interconnect lines to form a first series of thicker metal interconnect lines on top of said first pattern of thin-film metallic interconnect lines in said first series of trenches, said first series of thicker metal interconnect lines and said first dielectric layer forming a first substantially planer surface.
Claim 3
Dependent Claim
145 words
A method as recited in Claim 1 further including the steps of: forming an intermediate dielectric layer on said first substantially planer surface; forming a second pattern of thin-film metallic interconnect lines on said intermediate layer; forming a second dielectric layer on the entire area of said intermediate layer covering said second pattern of thin-film metallic interconnect lines; removing a portion of said second dielectric layer from said intermediate layer only in areas which cover said second thin-film metallic interconnect lines to form a second series of trenches above each of said second thin-film metallic interconnect lines; electroplating said second thin-film metallic interconnect lines to form a second series of thicker metal interconnect lines on top of said second pattern of thin-film interconnect lines such that said second series of thicker metal interconnect lines and said second dielectric layer form a second substantially planer surface.
Claim 4
Dependent Claim
18 words
A method as recited in Claim 1 wherein said first dielectric layer is formed from a polymeric material.
Claim 5
Dependent Claim
14 words
A method as recited in Claim 3 wherein said polymeric material is a polyimide.
Claim 6
Dependent Claim
40 words
A method as recited in Claim 1 further comprising the step of: curing said first dielectric layer after forming said first layer and before electroplating said first pattern of thin-film metallic interconnect lines to partially cure said first dielectric layer.
Claim 7
Dependent Claim
36 words
6 . A method as recited in Claim 5 further comprising the step of: curing said first dielectric layer after electroplating said first pattern of metallic Interconnect lines to substantially totally cure said first dielectric layer.
Claim 8
Dependent Claim
29 words
A method as recited in Claim 1 wherein said step of removing said portion of said first dielectric layer includes the step of: plasma etching said first dielectric layer.
Claim 9
Dependent Claim
128 words
A method as recited in Claim 7 wherein said step of plasma etching said first dielectric layer further includes the steps of: forming a first layer of inorganic film on said first dielectric layer; etching said first layer of inorganic film in a first etching pattern defined by said first pattern of thin-film metallic interconnect lines whereby said first etching pattern and said first pattern of thin-film metallic interconnect lines are in alignment with one another and a portion of said first dielectric layer therebetween is exposed; subjecting said first layer of inorganic film and said exposed portion of said first dielectric layer to a plasma to cause said exposed portion of said dielectric layer to be removed to expose said first pattern of thin-film metallic interconnect lines.
Claim 10
Dependent Claim
42 words
A method as recited in Claim 1 wherein said first dielectric layer is photosensitive and said step of removing a portion of said first dielectric layer further includes the step of: photolithographically exposing and removing said portion of said first dielectric layer.
Claim 11
Dependent Claim
75 words
1 0. A method as recited in Claim 9 wherein said first dielectric layer is a photosensitive polyimide and said step of photolithographically exposing and removing said first dielectric layer further includes the steps of: exposing said photosensitive polyimide to form a first negative exposure pattern in negative alignment with said first pattern of thin-film metallic interconnect lines; and removing all unexposed photosensitive polyimide to expose the underlying first pattern of thin-film metallic interconnect lines.
Claim 12
Dependent Claim
31 words
A method as recited in Claim 10 wherein said step of removing all photosensitive polyimide further includes: immersing said photosensitive polyimide in a selective organic solvent which removes the nonexposed polymide.
Claim 13
Dependent Claim
64 words
A method as recited in Claim 1 wherein said first pattern of thin-film metallic interconnect lines are connected with one another in a path along a perimeter of said substrate and said method of fabricating thin-film multilayer interconnect signal planes further includes the step of: destroying said path along said perimeter of said substrate after forming said first series of thicker metallic interconnect lines.
Claim 14
Dependent Claim
35 words
13 . A method as recited in Claim 1 further including the step of: forming metallic vias between said first series of thicker metal interconnect lines and said second pattern of thin-film metallic interconnect lines.
Claim 15
Dependent Claim
77 words
A method as recited in Claim 13 wherein said step of forming said vias includes: forming an intermediate dielectric layer over said first substantially planer surface; forming vias in said intermediate dielectric layer to expose portions of said first series of thicker metallic interconnect lines; and electroplating said portions of said first series of thicker metallic interconnect lines to produce metallic inserts wherein said metallic inserts and said third dielectric layer form an intermediate substantially planer surface.
Claim 16
Dependent Claim
24 words
A method as recited in Claim 1 wherein said thin-film metallic interconnect lines have a thickness in the range of 500 to 5,000 Angstroms.
Claim 17
Dependent Claim
24 words
A method as recited in Claim 1 wherein said thicker metal interconnect lines have a thickness in the range of 1 to 10 microns.
Claim 18
Independent Claim
76 words
A device for connecting semiconductor integrated circuits comprising: a substrate having a first substantially planer surface; and a first interconnect signal plane including a first pattern of metallic interconnect lines, each line being in the range of 1 to 10 microns thick and 5 to 20 microns wide, said interconnect lines being separated by a first dielectric material, said first dielectric material and said first pattern of metallic interconnect lines forming a second substantially planer surface.
Claim 19
Independent Claim
76 words
A device for connecting semiconductor integrated circuits comprising: a substrate having a first substantially planer surface; and a first interconnect signal plane including a first pattern of metallic interconnect lines, each line being in the range of 1 to 10 microns thick and 5 to 20 microns wide, said interconnect lines being separated by a first dielectric material, said first dielectric material and said first pattern of metallic interconnect lines forming a second substantially planer surface.
Claim 20
Dependent Claim
95 words
A device for connecting semiconductor integrated circuits as recited in Claim 17 further comprising: an intermediate dielectric layer on said second substantially planer surface; and a second interconnect signal plane on said second substantially planer surface, said second interconnect signal plane including a second pattern of metallic interconnect lines, each line being in the range of 1 to 10 microns thick and 5 to 20 microns wide, said second interconnect lines being separated by a second dielectric material, said second dielectric material and said second pattern of metallic interconnect lines forming a substantially planer surface.
Claim 21
Dependent Claim
26 words
A device for connecting semiconductor integrated circuits as recited in Claim 18 further comprising: metallic vias between said first and second pattern of metallic interconnect lines.
Claim 22
Dependent Claim
12 words
Any and all features of novelty described, referred to, exemplified, or shown.
Claim 23
Dependent Claim
12 words
Any and all features of novelty described, referred to, exemplified, or shown.
References Cited (Backward Citations)
No citation records indexed.
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