Planar semiconductor device having a field plate electrode

Claim 2

A semiconductor memory device comprising: a first semiconductor layer (14, 54) of a first conductivity type; a semiconductor region (15, 55) of a second conductivity type formed in said first semiconductor layer, said first semiconductor layer and said semiconductor region defining therebetween a planar junction; an insulation layer (19) formed of a predetermined pattern on said first semiconductor layer and said semiconductor region; and a second semiconductor layer (20) formed on said insulation layer, constituting a field plate electrode layer (20), said second semiconductor layer, when viewed through said insulation layer, extending from the periphery of said semiconductor region to said first semiconductor layer, characterized in that said second semiconductor layer comprises a first semiconductor portion (22) of said second conductivity type and a second semiconductor portion (23) of said first conductivity type, said first semiconductor portion is on the side of said semiconductor region (15, 55), when viewed through said insulation layer, said second semiconductor portion is on the side of said first semiconductor layer, when viewed through said insulation layer, and said first and second semiconductor portions define therebetween a junction extending over the entire thickness of said second semiconductor layer.

Claim 3

A semiconductor device according to claim 1, characterized by further comprising a second semiconductor region (16, 56) of said first conductivity type formed in said first recited semiconductor region, said second semiconductor region and said first semiconductor region (15, 55) defining therebetween a junction.

Claim 4

A semiconductor device according to claim 2, characterized in that said first semiconductor layer (14) constitutes the collector region of a bipolar transistor, said first semiconductor region (15) constitutes the base region of said bipolar transistor, and said second semiconductor region (16) constitutes the emitter region of said bipolar transistor.

Claim 5

A semiconductor device according to claim 1, characterized in that said planar junction defined between said first semiconductor layer (14, 54) ana said first recited semiconductor region (15, 55) is reverse biased, and said junction defined between saia first semiconductor portion.(22) and said second semiconductor portion (23) is reverse biased.

Claim 6

A semiconductor device according to claim 2, characterized in that said planar junction defined between said first semiconductor layer (14, 54) and said first recited semiconductor region (15, 55) is reverse biased, said junction defined between said first semiconductor portion (22) and said second semiconductor portion (23) is reverse biased, and said junction defined between said first recited semiconductor region (15, 55) and said second semiconductor region (16, 56) is forward biased.

Claim 7

A semiconductor device according to claim 1, characterized in that said second semiconductor layer (20) is made of polysilicon.

Claim 8

A semiconductor device according to claim 2, characterized in that said first semiconductor layer ( 54 ) constitutes the drain region of a MOS transistor, said first semiconductor region (55) constitutes the back-gate region of said MOS transistor, and said secona semiconductor region (56) constitutes the source region of said MOS transistor.

Claim 9

A semiconductor device according to claim 7, characterized by further comprising a gate electroae formed on said insulation layer (19) and above that portion of said back-gate region which is between saia first semiconductor layer (54) and said second semiconductor region (56), said gate electrode being provided at a same step for forming said second semiconductor layer (20) by patterning a same semiconductor layer.

Claim 10

A semiconductor device comprising: a first semiconductor layer (14, 54) of a first conductivity type; a semiconductor region (15, 55) of a second conductivity type formed in said first semiconductor layer, said first semiconductor layer and said semiconductor region defining therebetween a planar junction; an insulation layer (19) of a predetermined pattern formed on said first semiconductor layer and said semiconductor region; and a second semiconductor layer (20) formed on said insulation layer, constituting a field plate electrode layer (20), said second semiconductor layer, when viewed through said insulation layer, extending from the periphery of said semiconductor region to said first semiconductor layer, characterized in that said second semiconductor layer comprises a plurality of first semiconductor portions (22) of said second conductivity type and a plurality of second semiconductor portions (23) of said first conductivity type, said first semiconductor portions and said second semiconductor portions are, when viewed through said insulation layer, alternated from the periphery of said semiconductor region towards said first semiconductor layer so that a plurality of junctions is provided therebetween, said plural junctions include a plurality of junctions each of which is defined between one of said first semiconductor portions and that one or saia second semiconductor portions which is adjacent to saia one of said first semiconductor portions, said one of said first semiconductor portions is on the side of said semiconductor region, when viewed through said insulation layer, said that one of saia secona semiconductor portions is on the side of said first semiconductor layer, when viewed through said insulation layer, and said last recited plural junctions extend over the entire thickness of said second semiconductor layer.

Claim 11

A semiconductor device comprising: a first semiconductor layer (14, 54) of a first conductivity type; a semiconductor region (15, 55) of a second conductivity type formed in said first semiconductor layer, said first semiconductor layer and said semiconductor region defining therebetween a planar junction; an insulation layer (19) of a predetermined pattern formed on said first semiconductor layer and said semiconductor region; and a second semiconductor layer (20) formed on said insulation layer, constituting a field plate electrode layer (20), said second semiconductor layer, when viewed through said insulation layer, extending from the periphery of said semiconductor region to said first semiconductor layer, characterized in that said second semiconductor layer comprises a plurality of first semiconductor portions (22) of said second conductivity type and a plurality of second semiconductor portions (23) of said first conductivity type, said first semiconductor portions and said second semiconductor portions are, when viewed through said insulation layer, alternated from the periphery of said semiconductor region towards said first semiconductor layer so that a plurality of junctions is provided therebetween, said plural junctions include a plurality of junctions each of which is defined between one of said first semiconductor portions and that one or saia second semiconductor portions which is adjacent to saia one of said first semiconductor portions, said one of said first semiconductor portions is on the side of said semiconductor region, when viewed through said insulation layer, said that one of saia secona semiconductor portions is on the side of said first semiconductor layer, when viewed through said insulation layer, and said last recited plural junctions extend over the entire thickness of said second semiconductor layer.

Claim 12

A semiconductor device according to claim 9, characterized by further comprising a second semiconductor region (16, 56) of said first conductivity type formed in said first recited semiconductor region, said second semiconductor region and said first semiconductor region (15, 55) defining therebetween a junction.

Claim 13

A semiconductor device according to claim 10, characterized in that said first semiconductor layer

Claim 14

(14) constitutes the collector region of a bipolar transistor, said first semiconductor region (15) constitutes the base region of said bipolar transistor, and said second semiconductor region (16) constitutes the emitter region of said bipolar transistor.

Claim 15

(14) constitutes the collector region of a bipolar transistor, said first semiconductor region (15) constitutes the base region of said bipolar transistor, and said second semiconductor region (16) constitutes the emitter region of said bipolar transistor.

Claim 16

A semiconductor device according to claim 9, characterized in that said planar junction defined between said first semiconductor layer (14, 54) and said first recited semiconductor region (15, 55) is reverse biased, and the said last recited plural junctions defined between said first semiconductor portions (22) and said second semiconductor portions (23) are reverse biased.

Claim 17

A semiconductor device according to claim 10, characterized in that said planar junction defined between said first semiconductor layer (14, 54) and said first recited semiconductor region (15, 55) is reverse biased, the said last recited plural junctions defined between said first semiconductor portions (22) and said second semiconductor portions (23) are reverse biased, • . and said junction defined between said first recited semiconductor region (15, 55) and said second semiconductor region (16, 56) is forward biased.

Claim 18

A semiconductor device accorcinc to claim 9, characterized in that said second semiconductor layer

Claim 19

(20) is made of polysilicon.

Claim 20

(20) is made of polysilicon.

Claim 21

A semiconductor device according to claim 10, characterized in that said first semiconductor layer

Claim 22

(54) constitutes the drain region of a MOS transistor, said first semiconductor region (55) constitutes the back-gate region of said MOS transistor, and said second semiconductor region (56) constitutes the source region of said MOS transistor.

Claim 23

(54) constitutes the drain region of a MOS transistor, said first semiconductor region (55) constitutes the back-gate region of said MOS transistor, and said second semiconductor region (56) constitutes the source region of said MOS transistor.

Claim 24

A semiconductor device according to claim 15, characterized by further comprising a gate electrode formed on said insulation layer (19) and above that portion of said back-gate region which is between said first semiconductor layer (54) and said second semiconductor region (56), said gate electrode being provided at a same step for forming said second semiconductor layer (20) by patterning a same semiconductor layer.