§
Luxuse
Patent Intelligence
Sign In
← Back to Patent Explorer
EP0190027A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Semiconductor integrated circuit

Assignee: Toshiba Corp
•
Filing: 1986-01-27
•
Granted: —
•
Expires: 2006-01-27
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Semiconductor integrated circuit of the present invention comprises a signal output terminal (13, 21), a load circuit (11, 22, 26) connected to the signal output terminal (13,21), a a transistor circuit (12, 23) which is constituted by at least one first channel MOS transistor (12) and has an output terminal (N13) connected to the signal output terminal (13, 21) and an input terminal (N11) connected to a signal input terminal, and a first channel enhancement type MOS transistor (14, 24) that is inserted between the output terminal (N13) of the transistor circuit and the signal output terminal (13) and is normally in an on state. The present invention provides a highly reilable semiconductor integrated circuit in which no deterioration of characteristics due to hot carriers occurs even when the circuit is constituted using short channel MOS transistors with an effective channel lenght of about 1 micron or less.

Inventors

  • 👤 Takayasu C/O Patent Division Sakurai
  • 👤 Tetsuya C/O Patent Division Iizuka

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-02 12:26
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C5/00; G11C5/14; G11C7/1078; G11C7/1084; G11C7/22; G11C8/00; G11C8/08; H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0013; H03K19/003; H03K19/00315; H03K19/00346; H03K19/00361; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 97 words
(1) Semiconductor integrated circuit comprising a signal output terminal (13)(21), a load circuit (11)(22)(26) connected to said signal output terminal (13)(21), a transistor circuit (12)(23) which is constituted by at least one first channel MOS transistor (12) and has an output terminal (N13) connected to said signal output terminal (13)(21) and an input terminal (N11) connected to a signal input terminal, characterised in that a first channel enhancement type MOS transistor (14)(24) is inserted between said output terminal (N13) of said transistor circuit and said signal output terminal (13) and is made normally in an on state.
Claim 2
Dependent Claim 22 words
(2) Semiconductor integrated circuit as claimed in claim 1, wherein said first channel MOS transistor (12)(14)(24) is an n channel MOS transistor.
Claim 3
Dependent Claim 40 words
(3) Semiconductor integrated circuit as claimed in claim 1 or 2, wherein theeffective channel length of said MOS transistor constituting said transistor circuit (12)(23) and said first channel enhancement type MOS transistor (12) (24 is about 1 micron or less.
Claim 4
Dependent Claim 24 words
(4) Semiconductor integrated circuit as claimed in claim 1, wherein said load circuit (11)(22)(26) is constituted by at least one p channel MOS transistor.
Claim 5
Dependent Claim 28 words
(5) Semiconductor integrated circuit as claimed in claim 1, wherein said signal output terminal (56)(62) is set at a voltage which is higher than the power supply voltage.
Claim 6
Dependent Claim 22 words
(6) Semiconductor integrated circuit as claimed in claim 1, wherein an outer input signal is directly input into said signal input terminal.
Claim 7
Dependent Claim 22 words
(7) Semiconductor integrated circuit as claimed in claim 1, wherein an outer output signal is directly output from said signal output terminal.
Claim 8
Dependent Claim 47 words
1 (8) Semiconductor integrated circuit as claimed in claim 1, wherein said semiconductor integrated circuit is driven by at least two power supply systems and said first channel enhancement type MOS transistor is used in at least a higher power supply system within said power supply systems.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag