EP0189943A2 — Parallel image processor

Claim 1

Independent Claim 85 words

1 . A parallel image processor consisting of at least one main module (10) for performing a parallel operation of local neighboring image data on the basis of input image data externally taken in, comprising: at least one data memory (20-i) for delaying the input image data by one line of the data in order; and an output port (55) for fetching the delayed image data and feeding it to the other main module as an input image data for connection between the main modules.

Claim 2

Dependent Claim 85 words

1 . A parallel image processor consisting of at least one main module (10) for performing a parallel operation of local neighboring image data on the basis of input image data externally taken in, comprising: at least one data memory (20-i) for delaying the input image data by one line of the data in order; and an output port (55) for fetching the delayed image data and feeding it to the other main module as an input image data for connection between the main modules.

Claim 3

Dependent Claim 96 words

A parallel image processor consisting of at least one main module for performing a parallel operation of local neighboring image data on the basis of externally input image data, comprising: at least one data memory (20-i) for delaying the input image data by one line of the data in order; a selector (70) for selectively switching the externally input image data and the delayed image data; and an output port (55) for fetching the selected image data and feeding it to the other main module as an input image data for connection between the main modules.

Claim 4

Dependent Claim 96 words

A parallel image processor consisting of at least one main module for performing a parallel operation of local neighboring image data on the basis of externally input image data, comprising: at least one data memory (20-i) for delaying the input image data by one line of the data in order; a selector (70) for selectively switching the externally input image data and the delayed image data; and an output port (55) for fetching the selected image data and feeding it to the other main module as an input image data for connection between the main modules.

Claim 5

Dependent Claim 69 words

A parallel image processor as claimed in Claim 1 or 2, wherein said main module comprises: at least one sequential memory means (31-i) for storing local neighboring image data sequentially cut out from the input image data; a parallel operation unit (30) for performing a parallel operation of the local image data, and unifying means (40) for unifying the results of the parallel operation and outputting the unified result.

Claim 6

Dependent Claim 79 words

A parallel image processor as claimed in Claim 3, wherein said parallel operation unit (30) consists of a plurality of processor elements (37-i) and a plurality of coefficient memories for storing coefficient data corresponding to the processor elements, said sequential memory means (31-i) consists of a plurality of memory elements corresponding to the processor elements,and the local image data cut out from the sequential memory means and the coefficient data are operated in parallel in the corresponding processor elements.

Claim 7

Dependent Claim 19 words

A parallel image processor as claimed in Claim 3, wherein said sequential memory means is constructed by shift registers.

Claim 8

Dependent Claim 23 words

A parallel image processor as claimed in Claim 1 or 2, wherein said data memory is constructed by RAM's or by shift registers.

Claim 9

Dependent Claim 132 words

A parallel image processor consisting of at least one main module (10) for performing the parallel operation of m x n (m, n : integer) local neighboring image data cut out from an externally input image data, comprising: at least (m - 1) line buffer (20-i) for delaying said input image data in order by one line of the data; sequential memory means (30-i) consisting of m x n steps, for storing the local neighboring image data sequentially cut out from the input image data or the delay image data; a parallel operation section (30) including m processor elements for performing the parallel operation of the local neighboring image data; and a unifying circuit (40) for unifying the results of the parallel operation in n machine cycles and outputting the unified result.

Claim 10

Dependent Claim 132 words

A parallel image processor consisting of at least one main module (10) for performing the parallel operation of m x n (m, n : integer) local neighboring image data cut out from an externally input image data, comprising: at least (m - 1) line buffer (20-i) for delaying said input image data in order by one line of the data; sequential memory means (30-i) consisting of m x n steps, for storing the local neighboring image data sequentially cut out from the input image data or the delay image data; a parallel operation section (30) including m processor elements for performing the parallel operation of the local neighboring image data; and a unifying circuit (40) for unifying the results of the parallel operation in n machine cycles and outputting the unified result.

Claim 11

Dependent Claim 33 words

8 . A parallel image processor as claimed in Claim 7 , wherein said parallel operation section (30) comprises m coefficient memories (36-i) for coefficient data corresponding to the processor elements (37), respectively.

Claim 12

Dependent Claim 220 words

A parallel image processor consisting of at least one main module (10) for performing a parallel operation of local neighboring image data cut out from an externally input image data, comprising: an input port (54) for externally taking in an input image data; at least (m - 1) line buffers for delaying the input image data in order by one line of the data; m sequential memory means having a variable number of steps, for storing the local neighboring image data sequentially cut out from the input image data or the delayed image data; first (m - 1) selectors (33-i) for selectively switching the outputs from the line buffers and the outputs from the sequential memory means and supplying them to a succeeding sequential memory means; a parallel operation section (30) comprising m processor elements (37) for performing the parallel operation of the local neighboring image data output from the corresponding sequential memory means; unifying means (40) for unifying the results of the parallel operation and outputting the unified result; a second selector (70) for selectively switching the externally input image data and the image data delayed by the line buffers; an output port (55) for fetching the image data selected by the second selector; and a control circuit (21) for supplying control signals to said first and second selectors.

Claim 13

Dependent Claim 220 words

A parallel image processor consisting of at least one main module (10) for performing a parallel operation of local neighboring image data cut out from an externally input image data, comprising: an input port (54) for externally taking in an input image data; at least (m - 1) line buffers for delaying the input image data in order by one line of the data; m sequential memory means having a variable number of steps, for storing the local neighboring image data sequentially cut out from the input image data or the delayed image data; first (m - 1) selectors (33-i) for selectively switching the outputs from the line buffers and the outputs from the sequential memory means and supplying them to a succeeding sequential memory means; a parallel operation section (30) comprising m processor elements (37) for performing the parallel operation of the local neighboring image data output from the corresponding sequential memory means; unifying means (40) for unifying the results of the parallel operation and outputting the unified result; a second selector (70) for selectively switching the externally input image data and the image data delayed by the line buffers; an output port (55) for fetching the image data selected by the second selector; and a control circuit (21) for supplying control signals to said first and second selectors.

Claim 14

Dependent Claim 56 words

A parallel image processor as claimed in Claim 9 , wherein said parallel operation section (30) comprises m coefficient memories for coefficient data corresponding to the processor elements (37), respectively, and the local neighboring image data cut out from the sequential memory means and the coefficient data are operated in parallel in the corresponding processor elements.

Claim 15

Dependent Claim 32 words

A parallel image processor as claimed in Claim 9 , wherein said sequential memory means intermittently performs a shift operation for clock signals and reads out the memory content each clock signal.

Claim 16

Dependent Claim 88 words

A parallel image processor as claimed in Claim 9 , wherein said line buffers comprise information memory sections (241, 242) permitting at least one bit to be simultaneously read out and written in, and a row address control section (245) for cont-olling the row addresses of said information memory section, the read-out, write-in starting and ending row addresses of said information memory section are determined in accordance with the control signals supplied to the row address control section so as to make variable the number of delay steps.

Claim 17

Dependent Claim 56 words

A parallel image processor as claimed in Claim 9, further comprising an operation data input port (64) for taking in an operation result externally provided which is unified with the operation result obtained from the parallel operation section in said unifying means (40), and an operation data output port (65) for externally outputting the unified result.

Claim 18

Dependent Claim 58 words

A parallel image processor as claimed in Claim 9, wherein each of said sequential memory means in said main module is constructed by n steps and said first selectors are switched to the outputs from the line buffers, so that m x n local neighboring image data are processed in a time division manner in n machine cycles.

Claim 19

Dependent Claim 94 words

A parallel image processor as claimed in Claim 9, wherein consisting of n main modules n x m local neighboring image data are processed during one machine cycle in such a state that the image data output ports (55) are connected with the input ports of succeeding main modules to provide the sequential memory means each having one step, the first selectors (33-i) are switched to the outputs from the sequential memory means, and the second selector (70) is switched to the output from the line buffer delayed by one line of the data.

Claim 20

Dependent Claim 99 words

A parallel image processor as claimed in Claim 9, an arrangement wherein consisting of n main modules maximum (m x n) x t local image neighboring image data are processed in a time division manner in t machine cycles in such a state that the image data output ports are connected with the input ports of secceeding main modules to provide the sequential memory means each having t steps, the first selectors (33-i) are switched to the outputs from the line buffer, and the second selector (70) is switched to either one of the outputs from the line buffers.

Parallel image processor

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