Memory unit having arithmetic and logic functions, in particular for graphic processing

Claim 2

A memory circuit having memory elements (2) on which operations to read, to write, and to store data can be arbitrarily effected characterized by comprising control circuit means (1) having: a first mode in which, based on a first data ( Y ) from a device located externally with respect to said memory elements (2) and a second data (Do) in said memory elements (2), said first data (Y) is stored in said memory elements (2); a second mode in which said second data (Do) is stored again in said memory elements (2); and a third mode in which an inverted data (Do) obtained by inverting said second data (Do) is stored again in said memory elements (2).

Claim 3

A memory circuit according to Claim 1 wherein each said mode in said control circuit means (1) is selected by use of a third data (X) from a device located externally with respect to said memory elements (2); and said third data (X) is utilized to discriminate said first mode from said second and third modes, and said first data (Y) is utilized to discriminate said second mode from said third mode, thereby updating said second data to be a desired value.

Claim 4

A memory circuit according to Claim 1 wherein said first mode is utilized to store said first data (Y) in said memory elements (2) at a location where said second data (Do) is stored previously; said second mode is utilized to store said second data (Do) again in said memory elements (2) at a location where said second data (Do) is stored previously; and said third mode is utilized to store an inverted data ( Do ) obtained by inverting said second data (Do) in said memory elements (2) at a location where said second data (Do) is stored previously.

Claim 5

A memory circuit according to Claim 2 further comprising a first selector (SEL0̸) and a second selector (SEL1) for selecting data items as said third data (X) and as said first data (Y), respectively from a plurality of inputs ("0", "1", Di, Di) based on a preset condition; an output from said first selector (SEL0̸) being said first data (Y); an output from said second selector (SEL1) being said third data (X); and said first and second selectors (SEL0̸, SELl) each being independently controllable for the select operation.

Claim 6

A memory circuit according to Claim 4 wherein said first and second selector (SEL0̸, SEL1) each are provided with four inputs; said four inputs including a fixed logic value "0", a fixed logic value "1", a fourth input (Di) the value of which can be arbitrarily changed to be a logic value "0" or "1", and an inverted value obtained by inverting said fourth data (Di); and said first and second selectors (SEL0̸, SEL1) each independently control for the selection of said four input data items so as to combine said first and third data (Y, X) outputted from said selectors (SELØ, SELl), thereby effecting a dyadic logic operation.

Claim 7

A memory circuit according to Claim 1 further comprising: selector means (SEL2) for selecting on an input port side either said second data (Do) from an output port or said fourth data (Di) from an external device; and priority control circuit means (4) from which a control signal (S4) for controlling said selector (SEL2) is extracted by use of said second data (Do) from the output port, said fourth data (Di) from the external device, and a priority specification signal for selecting either said second data (Do) obtained from the output port via an external device or said fourth data (Di) from the external device.

Claim 8

A memory circuit according to Claim 6 wherein: said fourth data (Di) from the external device and said second data (Do) from the output port are subdivided into two regions comprising a section said data (Di, Do) of which is actually to be stored and the other section; said priority control circuit means (4) causes said selector means (SEL2) to select said fourth data (Di) from the external device when said priority specification signal (P) specifies said fourth data (Di) in a processing of said region in which said fourth data (Di) from the external device and said second data (Do) from the output port are to be actually stored and to cause the selector means (SEL2) to select said second data (Do) when said priority specification signal (P) specifies said second data (Do) from the output port in said processing; and to cause said selector means (SEL2) to select said second data (Do) in a processing of a region in which neither said fourth data (Di) nor said second data (Do) are to be actually stored, to cause said selector means (SEL2) to select said fourth data (Di) in a processing of a section in which only said fourth data (Di) is to be actually stored; and to cause the selector means (SEL2) to select said second data (Do) from the output port in a processing of a section in which only said second data (Do) is to be actually stored.

Claim 9

A memory circuit according to Claim 2 wherein said memory elements (2) and said control circuit means (1) are arbitrarily arranged with an arbitrary data length (number of bits) or an arbitrary data capacity.

Claim 10

A memory circuit according to Claim 8 wherein a group of said memory elements.(2) and a group of said control circuit means (1) each arbitrarily arranged are manufactured in a same LSI chip.

Claim 11

A memory circuit according to Claim 5 wherein said memory elements (2), said control circuit means (1), and said two selectors (SEL0, SEL1) are arbitrarily arranged with an arbitrary data length (number of bits) or an arbitrary data capacity.

Claim 12

A memory circuit according to Claim 10 wherein a group of said memory elements (2), a group of said control circuit means (1), and said two selector means (SEL0, SELl) each are manufactured in a same LSI chip.

Claim 13

A memory circuit according to Claim 4 comprising means having a function equivalent to a function developed by a combination of said control circuit means (1) and said two selector means. (SELØ, SELl).

Claim 14

A memory circuit according to Claim 12 wherein said means is arbitrarily arranged with an arbitrary data length (number of bits) or an arbitrary data capacity.

Claim 15

A memory circuit according to Claim 13 wherein a group of said means is manufactured in a same LSI chip.

Claim 16

A memory circuit having memory element (2) on which operations to read, to write, and to store data can be arbitrarily effected characterized by comprising control circuit means (1') having: a first mode in which, based on a first data (Y) from a device located externally with respect to said memory elements (2) and a second data (Do) in said memory elements (2), said first data (Y) is stored in said memory elements (2); and a second mode in which an operation result data (Z) obtained from an arithmetic operation conducted on said first data (Y) and said second data (Do) is stored in said memory elements (2).

Claim 17

A memory circuit having memory element (2) on which operations to read, to write, and to store data can be arbitrarily effected characterized by comprising control circuit means (1') having: a first mode in which, based on a first data (Y) from a device located externally with respect to said memory elements (2) and a second data (Do) in said memory elements (2), said first data (Y) is stored in said memory elements (2); and a second mode in which an operation result data (Z) obtained from an arithmetic operation conducted on said first data (Y) and said second data (Do) is stored in said memory elements (2).

Claim 18

A memory circuit according to Claim 15 wherein said two modes are discriminated from each other by one of said control input signals (CNT) from external devices.

Claim 19

A memory circuit according to Claim 16 wherein said two modes include said first mode and said second mode.

Claim 20

A memory circuit according to Claim 17 wherein one of said control input signals from an external devices is a carry input signal (Cr).

Claim 21

A memory circuit according to Claim 15 wherein said first data (Y) and said second data (Do) are added with a carry operation in an arithmetic operation in said second mode.

Claim 22

A memory circuit according to Claim 19 wherein a result of said addition with a carry operation effected on said second data (Do) is outputted.

Claim 23

A memory circuit according to Claim 15 further comprising: two selector means (SEL3, SEL4) each for selecting a data item (X, Y) from a plurality of input data items, an output from a first selector means (SEL4) of said selector means being an input of said first data (Y), an output from a second selector means (SEL3) thereof being input of one of said control input signals (Cr) from external devices, and said two selectors (SEL0, SELl) each execute output selection independent of each other.

Claim 24

A memory circuit according to Claim 21 wherein input data to said first selector (SELØ) in said second mode includes said first data (Di) from an external device and an inverted data (Di) thereof, and input data to said second selector (SELl) includes 0 and 1.

Claim 25

A memory circuit having memory elements (2) on which operations to read, to write, and to store data can be arbitrarily effected characterized by comprising control circuit means (1') having: an ordinary write mode in which, based on a first data (Y) from an external device and a second data (Do) in said memory elements (2), said first data (Y) is stored in said memory elements (2); a logic operation mode in which data (Z) obtained as a result of a logical operation conducted between said first data (Y) and said second data (Do) is stored in said memory elements (2); and an arithmetic operation mode in which data (Z) obtained as a-result of an arithmetic operation conducted between said first data (Y) and said second data (Do) is stored in said memory elements (2).

Claim 26

A memory circuit having memory elements (2) on which operations to read, to write, and to store data can be arbitrarily effected characterized by comprising control circuit means (1') having: an ordinary write mode in which, based on a first data (Y) from an external device and a second data (Do) in said memory elements (2), said first data (Y) is stored in said memory elements (2); a logic operation mode in which data (Z) obtained as a result of a logical operation conducted between said first data (Y) and said second data (Do) is stored in said memory elements (2); and an arithmetic operation mode in which data (Z) obtained as a-result of an arithmetic operation conducted between said first data (Y) and said second data (Do) is stored in said memory elements (2).

Claim 27

A memory circuit according to Claim 23 wherein said three modes in said control circuit means (1') each are specified by a plurality of control input signals (CNT, Cr) from external devices.

Claim 28

A memory circuit according to Claim 23 wherein said three modes of said control circuit means (1') each are specified by two control input signals (CNT, Cr) from external devices.

Claim 29

A memory circuit according to Claim 25 wherein said three modes are classified into two kinds of modes by one (CNT) of said control input signals from external devices.

Claim 30

A memory circuit according to Claim 26 wherein said two kinds of modes include the ordinary write mode on a group of said logical operation mode and said arithmetic operation mode.

Claim 31

A memory circuit according to Claim 26 wherein one of said control input signals from external devices in the arithmetic operation mode is a carry input signal (Cr).

Claim 32

A memory circuit according to Claim 27 wherein said ordinary write mode is discriminated from said logical operation mode by a control input signal (CNT) different from said external control input signal (Cr) specified to discriminate said two kinds of modes.

Claim 33

A memory circuit according to Claim 23 wherein said first data (Y) and said second data (Do) are subjected to an exclusive OR operation as a logic operation in said logic operation mode.

Claim 34

A memory circuit according to Claim 23 wherein said first data (Y) and said second data (Do) are added with a carry operation in an operation in said arithmetic operation mode.

Claim 35

A memory circuit according to Claim 31 wherein a carry result obtained from said arithmetic addition with a carry operation conducted in the arithmetic operation mode is outputted.

Claim 36

A memory circuit according to Claim 24 further comprising: two selector means (SEL3, SEL4) each for selecting a data item (X, Y) from a plurality of input data items, an output from a first selector means (SEL4) of said selector means being an input of said first data (Y), an output from a second selector means (SEL3) thereof being an input of one of said control input signals from external devices; and output selections of said two selectors (SEL3, SEL4) each are specified independently of each other.

Claim 37

A memory circuit according to Claim 28 wherein said carry input signal (Cr) is identical to the control signal for discriminating said ordinary write mode from said logic operation mode.