Data stream synchronisers

Claim 2

A synchronizer for converting a first data stream provided at a first predetermined data rate to a second data stream provided at a second predetermined data rate, said synchronizer comprising: a) elastic buffer means for receiving said first data stream and for providing said second data stream; and b) means for controlling said elastic buffer including means for synchronizing the control of said elastic buffer with said first and second data rates so as to avoid the occurrence and propagation of metastable logic states.

Claim 3

The synchronizer of Claim 1 wherein the conversion of said first. data stream to said second data stream is subject to a fault condition and wherein said control means further comprises means for determining the occurrence of said fault condition and for providing a signal in response thereto.

Claim 4

The synchronizer of Claim 2 wherein said determining means is further characterized as determining the occurrence of said fault condition prior to its actual occurrence.

Claim 5

The synchronizer of Claim 3 wherein said control means further includes means for initializing said elastic buffer, said initializing means being coupled with said control synchronizing means so as to properly initialize said elastic buffer for the provision of said second data stream with respect to said first data stream.

Claim 6

The synchronizer of Claim 4 wherein said first and said second data streams are further characterized as serial data streams.

Claim 7

. The synchronizer of Claim 3 or 5 wherein said elastic buffer means comprises: a) buffer means for storing data at a plurality of memory locations; and b) pointer means for asynchronously directing the writing of data from said first data stream to said buffer means and for reading said second data stream from said buffer.

Claim 8

The synchronizer of Claim 6 wherein said determining means further comprises; a) status means for maintaining a current status indicator for each of said memory locations of said elastic buffer; and b) means for checking said status indicators, said checking means being coupled with said pointer means so as to provide a signal indicating whether said fault condition will occur with the next successive reading or writing of said buffer in response to said pointer means.

Claim 9

A data stream synchronizer comprising: a) data storing means for storing data at a plurality of memory locations; b) writing means for writing data to said storing means; c) reading means for reading data from said storing means asynchronously with respect to said writing means; and d) determining means for determining the imminent occurrence of an overflow/underflow condition and providing a signal in response thereto.

Claim 10

A data stream synchronizer comprising: a) data storing means for storing data at a plurality of memory locations; b) writing means for writing data to said storing means; c) reading means for reading data from said storing means asynchronously with respect to said writing means; and d) determining means for determining the imminent occurrence of an overflow/underflow condition and providing a signal in response thereto.

Claim 11

The data stream synchronizer of Claim 8 further comprising status storing means for storing the status of the respective memory locations of said data storing means, the status stored reflecting the writing or reading of data to one of said memory locations.

Claim 12

The data stream synchronizer of Claim 9 wherein said determining means is further characterized as being coupled to said status storing means for determining the status of said memory locations as data is written to and read from said memory locations.

Claim 13

The data stream synchronizer of Claim 8 or 10 wherein said determining means is further characterized as determining the imminent occurrence of an overflow/underflow condition when an actual overflow/underflow condition would occur with the next successive writing or reading of data by said writing or reading means, respectively.

Claim 14

The data stream synchronizer of Claim 10 wherein said writing and said reading means are further characterized as writing and reading data from respectively logically successive memory locations of said data storing means.

Claim 15

The data stream synchronizer of Claim 12 wherein said determining means includes status checking means for testing the status associated with each one of said memory locations and the status of their respective logically adjacent memory locations so as to determine the imminent occurrence of an overflow/underflow condition prior to its actual occurrence.

Claim 16

The data stream synchronizer of Claim 13 wherein said status storing means includes a plurality of status flag locations that respectively store a status flag, each said status flag location corresponding to a respective memory location of said data storing means.

Claim 17

The data stream synchronizer of Claim 14 wherein said writing and said reading means respectively include means for altering said status flags, said flag altering means of said writing means providing for the alteration of the status flag associated with the one of said memory locations written to by said writing means, said status flag being altered to a first predetermined logic state.

Claim 18

The data stream synchronizer of Claim 15 wherein said flag altering means of said reading means provides for the alteration of the status flag associated with the one of said memory locations logically prior and adjacent the one of said memory locations read by said reading means, said status flag being altered to second predetermined logic state.

Claim 19

A serial data stream synchronizer comprising: a) a serial data buffer having a plurality of memory locations for storing data; b) a plurality of status bit latches, each said status latch being associated with a respective one of said memory locations of said buffer; c) a first counter for, establishing a data write pointer into said buffer; d) a second counter for establishing a data read pointer into said buffer; e) means for controlling the writing of data to memory locations in said buffer as pointed to by said first counter; f) means for controlling the reading of data from memory locations in said buffer as pointed to by said second counter; and g) status altering means for altering the respective status bits of said status latches, said status altering means being coupled with said first and said second counters for selecting the ones of said status bits to be altered.

Claim 20

A serial data stream synchronizer comprising: a) a serial data buffer having a plurality of memory locations for storing data; b) a plurality of status bit latches, each said status latch being associated with a respective one of said memory locations of said buffer; c) a first counter for, establishing a data write pointer into said buffer; d) a second counter for establishing a data read pointer into said buffer; e) means for controlling the writing of data to memory locations in said buffer as pointed to by said first counter; f) means for controlling the reading of data from memory locations in said buffer as pointed to by said second counter; and g) status altering means for altering the respective status bits of said status latches, said status altering means being coupled with said first and said second counters for selecting the ones of said status bits to be altered.

Claim 21

The synchronizer of Claim 17 wherein the data transfer rate of a first data stream is adjusted to match a predetermined data transfer rate, said synchronizer further comprising: a) means for initializing said buffer, said first and said second counters and said status latches; and b) means for synchronizing said write control means, said read control means and said initializing means each with respect to the data transfer rate of said first data stream and said predetermined data transfer rate so as to avoid the occurrence of metastable logic states.

Claim 22

A circuit for synchronizing a first control signal occurrence associated with a first clock signal with a second clock signal comprising: a) clock signal independent means for latching said first control signal and providing a second control signal in response thereto; b) first means for latching said second control signal and providing a third control signal in repsonse thereto, said first means being responsive to said second clock signal; and c) second means for latching said third control signal and providing a synchronized control signal in response thereto, said second means also being responsive to said second clock signal.

Claim 23

A circuit for synchronizing a first control signal occurrence associated with a first clock signal with a second clock signal comprising: a) clock signal independent means for latching said first control signal and providing a second control signal in response thereto; b) first means for latching said second control signal and providing a third control signal in repsonse thereto, said first means being responsive to said second clock signal; and c) second means for latching said third control signal and providing a synchronized control signal in response thereto, said second means also being responsive to said second clock signal.